Motorola GP series Informasi Layanan - Halaman 5

Jelajahi secara online atau unduh pdf Informasi Layanan untuk Radio Dua Arah Motorola GP series. Motorola GP series 30 halaman. Professional radio
Juga untuk Motorola GP series: Panduan Servis (26 halaman), Informasi Layanan (24 halaman), Informasi Layanan (31 halaman), Informasi Layanan (43 halaman), Panduan Pengguna (16 halaman), Manual (30 halaman)

Motorola GP series Informasi Layanan
1.0

Overview

This Chapter provides a detailed theory of operation for the power distribution and controller circuits
in the radio. The components for these circuits are contained on the Main Board. Refer to the RF
sections of this manual for the component location details and the parts lists for these circuits.
2.0

Radio Power Distribution

UNSWB+
Fuse
7.5V
Battery
3.5V
Reg.
LI Ion
PA, Driver
PCIC(ALC)
Figure 1-1 illustrates the DC distribution throughout the radio board. A 7.5V battery (BATT 7.5V)
supplies power directly to the electronic on/off control as UNSWB+. When the radio is turned on,
MECH_SWB+ (on/off/volume control) will trigger the electronic on/off control (momentary-on path),
then SWB+ is distributed as shown in Figure1-1. Vdda from 3.3V Vdda regulator will then supply the
microprocessor. Data is then sent to ASFIC_CMP to turn on GCB4(DAC). GCB4 will take over the
momentary-on path within 12ms. SWB+ will continue to support the whole board until the radio is
turned off.
Radio will be turned-off on two conditions;
1. MECH_SWB+ turned off
2. Low battery
When low battery level is detected by the microprocessor through both conditions above, it will store
the radio personality data to EEPROM before turning off.
Audio PA
R5
R1
SWB+
Control
MECH.
SWB+
On/Off Switch
Low Battery
Detect
Ant. SW
Figure 1-1 DC Power Distribution Block Diagram
THEORY OF OPERATION
Accessories
20 pin Connector
Keypad/Option Board
Prime Expansion Board
Int/Ext Vdd
R4
4.0V/3.3V
Vdda
Vdda
Reg.
R3
R2
Vddd
Vddd
Reg.
TX.
Led
MCU Micro P, ROM
& EEPROM
5V
Reg.
5V
Jumpers
R1
RF. AMP, IF AMP
Ext. RX.
R2
Buffer (NU)
R3
R4
R5
Vdda
SW. Reg.
Switching
Reg.
FRACTN
LCD
ASFIC_CMP
Driver
VCOBIC
Dual Vdd
Single Vdd
Regulator
Regulator
Scheme
Scheme
Y
Y
N
N
N
Y
N
N
Y
N
Y
N
N
N
Chapter 1
IF