MSI 610BF Manual - Halaman 24
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SDRAM RAS Precharge Time: If an insufficient number of cycles is allowed for the RAS
to accumulate its charge before DRAM refresh, the refresh may be incomplete and the
DRAM may fail to retain data. Fast gives faster performance; and Slow gives more stable
performance. This field applies only when synchronous DRAM is installed in the system.
The Choice: 2, 3.
System BIOS Cacheable: Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance. However, if any program writes
to this memory area, a system error may result.
The choice: Enabled, Disabled.
Video BIOS Cacheable: Select Enabled allows caching of the video BIOS , resulting in
better system performance. However, if any program writes to this memory area, a system
error may result.
The Choice: Enabled, Disabled.
Memory Hole At 15M-16M: You can reserve this area of system memory for ISA adapter
ROM. When this area is reserved, it cannot be cached. The user
information of peripherals that need to use this area of system memory usually
discusses their memory requirements.
The Choice: Enabled, Disabled.
Delay Transaction: The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.
The Choice: Enabled, Disabled.
On-Chip Video Window Size: Select the on-chip video window size for VGA drive use.
The Choice: 32MB, 64MB, Disabled.
Onboard Display Cache Setting: Setting the onboard display cache timing.
CAS # Latency: Select the local memory clock periods.
The Choice: 2, 3
Paging Mode Control: Select the paging mode control.
The Choice: Close, Open.
RAS-to-CAS Override: Select the display cache clock periods control.
The Choice: Close, Open.
RAS# Timing: This item controls RAS# active to Protegra, and refresh to RAS# active delay
( in local memory clocks).
The Choice: Fast, Slow.
RAS# Precharge Timing: This item controls RAS# precharge (in local memory clocks).
The choice: Fast, Slow.
3-4 Integrated Peripherals
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