Cypress Semiconductor CY25566 Lembar Spesifikasi - Halaman 7

Jelajahi secara online atau unduh pdf Lembar Spesifikasi untuk Perangkat Keras Komputer Cypress Semiconductor CY25566. Cypress Semiconductor CY25566 9 halaman. Cypress spread spectrum clock generator specification sheet

Absolute Maximum Ratings

Supply Voltage (V
: .......................................................+6V
DD
Operating Temperature: ...................................... 0°C to 70°C
Storage Temperature .................................. –65°C to +150°C
Table 4. DC Electrical Characteristics V
Parameter
Description
V
Power Supply Range
DD
V
Input High Voltage
INH
V
Input Middle Voltage
INM
V
Input Low Voltage
INL
V
Output High Voltage
OH1
V
Output High Voltage
OH2
V
Output Low Voltage
OL1
V
Output Low Voltage
OL2
C
Input Capacitance
in1
C
Input Capacitance
in2
C
Input Capacitance
in2
I
Power Supply Current
DD1
I
Power Supply Current
DD1
I
Power Supply Current
DD2
I
Power Supply Current
DD2
Table 5. Electrical Timing Characteristics V
Parameter
Description
I
Input Clock Frequency Range Non-crystal, 3.0V Pk–Pk ext. source
CLKFR
t
Clock Rise Time
RISE(a)
t
Clock Fall Time
FALL(a)
t
Clock Rise Time
RISE(a+b)
t
Clock Fall Time
FALL(a+b)
t
Clock Rise Time
RISE(a+b)
t
Clock Fall Time
FALL(a+b)
t
Clock Rise Time
RISE(REF)
t
Clock Fall Time
FALL(REF)
D
Input Clock Duty Cycle
TYin
D
Output Clock Duty Cycle
TYout
C
Cycle-to-Cycle Jitter
CJ1
C
Cycle-to-Cycle Jitter
CJ2
REFOUT
Refout Frequency Range
Note:
1.
Operation at any Absolute Maximum Rating is not implied.
2.
Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document #: 38-07429 Rev. *B
[1, 2]
= 3.3V, Temp. = 25°C, unless otherwise noted
DD
Conditions
±10%
S0 and S1 only.
S0 and S1 only.
S0 and S1 only.
I
= 6 ma, SSCLKa
OH
I
= 20 ma, SSCLKb
OH
I
= 6 ma, SSCLKa
OH
I
= 20 ma, SSCLKb
OH
Xin/CLK (Pin 1)
Xout (Pin 8)
All input pins except 1.
FIN = 40 MHz,15 pF@all outputs
FIN = 40 MHz, No Load
FIN = 165 MHz,15 pF@all outputs
FIN = 165 MHz, No Load
= 3.3V, T = 25°C and C
DD
Conditions
SSCLK1a or SSCLK1b, Freq = 100 MHz
SSCLK1a or SSCLK1b, Freq = 100 MHz
SSCLK1(a+b), CL = 33 pF, 100 MHz
SSCLK1(a+b), CL = 33 pF, 100 MHz
SSCLK1(a+b), CL = 33 pF, 200 MHz
SSCLK1(a+b), CL = 33 pF, 200 MHz
REFOUT, Pin 3, CL = 15 pF, 50 MHz
REFOUT, Pin 3, CL = 15 pF, 50 MHz
XIN/CLK (Pin)
SSCLK1a/b (Pin 8 and 9)
F = 100 MHz, SSCLK1a/b CL = 33 pF
F = 200 MHz, SSCLK1a/b CL = 33 pF
CL = 15 pF
Min.
Typ.
2.97
3.3
0.85V
V
DD
DD
0.40V
0.50V
DD
DD
0.0
0.0
2.4
2.0
3
4
6
8
3
4
27
21
68
48
= 15 pF, unless otherwise noted. Rise/Fall @ 0.4–2.4V,
L
Min.
25
1.0
1.0
1.2
1.2
1.1
1.1
1.0
1.0
30
45
25
CY25566
Max.
Unit
3.63
V
V
V
DD
0.60V
V
DD
0.15V
V
DD
V
V
0.4
V
1.2
V
5
pF
10
pF
5
pF
32
mA
28
mA
80
mA
60
mA
Typ.
Max
Unit
200
MHz
1.3
1.6
ns
1.3
1.6
ns
1.5
1.8
ns
1.5
1.8
ns
1.4
1.7
ns
1.4
1.7
ns
1.3
1.6
ns
1.3
1.6
ns
50
70
%
50
55
%
300
400
ps
500
600
ps
108
MHz
Page 7 of 9
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