Cypress Semiconductor CY7C024AV Lembar Spesifikasi

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Features
True dual-ported memory cells which enable simultaneous
access of the same memory location
4, 8 or 16K × 16 organization
[1]
(CY7C024AV/024BV
/ 025AV/026AV)
4 or 8K × 18 organization (CY7C0241AV/0251AV)
16K × 18 organization (CY7C036AV)
0.35 micron CMOS for optimum speed and power
High speed access: 20 and 25 ns
Low operating power
Active: I
= 115 mA (typical)
CC
= 10 μA (typical)
Standby: I
SB3
Logic Block Diagram
R/W
L
UB
L
CE
L
LB
L
OE
L
[2]
IO
–IO
8/9L
15/17L
[3]
IO
–IO
0L
7/8L
12/13/14
[4]
A
–A
0L
11/1213L
[4]
A
–A
0L
11/12/13L
CE
L
OE
L
R/W
L
SEM
L
[5]
BUSY
L
INT
L
UB
L
LB
L
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO
–IO
for x16 devices; IO
–IO
8
15
9
3. IO
–IO
for x16 devices; IO
–IO
0
7
0
8
4. A
–A
for 4K devices; A
–A
for 8K devices; A
0
11
0
12
5. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *J
8/9
8/9
IO
Control
Address
True Dual-Ported
Decode
12/13/14
for x18 devices.
17
for x18 devices.
–A
for 16K devices.
0
13
198 Champion Court
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Fully asynchronous operation
Automatic power down
Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
On chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Separate upper byte and lower byte control
Pin select for Master or Slave (M/S)
Commercial and industrial temperature ranges
Available in 100-pin Pb-free TQFP and 100-pin TQFP
IO
Control
Address
RAM Array
Decode
12/13/14
Interrupt
Semaphore
Arbitration
M/S
San Jose
Static RAM
R/W
R
UB
R
CE
R
LB
R
OE
[2]
8/9
IO
–IO
8/9L
15/17R
[3]
8/9
IO
–IO
0L
7/8R
12/13/14
[4]
A
–A
0R
11/12/13R
[4]
A
–A
0R
11/12/13R
CE
R
OE
R
R/W
R
SEM
R
[5]
BUSY
R
INT
R
UB
R
LB
R
,
CA 95134-1709
408-943-2600
Revised December 10, 2008
R
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