Cypress Semiconductor CY7C1012DV33 Lembar Spesifikasi

Jelajahi secara online atau unduh pdf Lembar Spesifikasi untuk Perangkat Keras Komputer Cypress Semiconductor CY7C1012DV33. Cypress Semiconductor CY7C1012DV33 12 halaman. 12-mbit (512k x 24) static ram

Halaman Cetak
Features
■
High speed
❐
t
= 10 ns
AA
■
Low active power
❐
I
= 175 mA at 10 ns
CC
■
Low CMOS standby power
❐
I
= 25 mA
SB2
■
Operating voltages of 3.3 ± 0.3V
■
2.0V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
■
Available in Pb-free standard 119-ball PBGA
Logic Block Diagram
A
(9:0)
Cypress Semiconductor Corporation
Document Number: 38-05610 Rev. *D

Functional Description

The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
controlled by the individual chip selects (CE
CE
1
data on I/O
I/O
16
that significantly reduces power consumption when deselected.
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE) input is LOW. Data on the respective input and output (I/O)
pins is then written into the location specified on the address pins
(A
– A
0
LOW writes all 24 bits of data into the SRAM. Output enable (OE)
is ignored while in WRITE mode.
Data bytes are also individually read from the device. Reading a
byte is accomplished when the chip select controlling that byte
is LOW and write enable (WE) HIGH, while output enable (OE)
remains LOW. Under these conditions, the contents of the
memory location specified on the address pins appear on the
specified data input and output (I/O) pins. Asserting all the chip
selects LOW reads all 24 bits of data from the SRAM.
The 24 I/O pins (I/O
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For more infor-
mation, see the
INPUT BUFFER
512K x 24
ARRAY
COLUMN
DECODER
CONTROL LOGIC
A
(18:10)
•
198 Champion Court
12-Mbit (512K X 24) Static RAM
controls the data on the I/O
– I/O
0
– I/O
, and CE
controls the data on the data pins
8
15
3
– I/O
. This device has an automatic power down feature
23
). Asserting all of the chip selects LOW and write enable
18
– I/O
) are placed in a high impedance
0
23
Truth Table
on page 8.
I/O
– I/O
0
7
I/O
– I/O
8
15
I/O
– I/O
16
CE
, CE
, CE
1
2
3
WE
OE
,
•
San Jose
CA 95134-1709
CY7C1012DV33
, CE
, and CE
).
1
2
3
, while CE
controls the
7
2
23
•
408-943-2600
Revised November 6, 2008
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