Cypress Semiconductor CY7C1330AV25 Lembar Spesifikasi - Halaman 3

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Pin Definitions
Name
I/O Type
A
Input-
Synchronous
BWS
Input-
a
BWS
Synchronous
b
BWS
c
BWS
d
WE
Input-
Synchronous
K,K
Input-
Differential Clock
CE
Input-
Synchronous
OE
Input-
Asynchronous
DQ
I/O-
a
DQ
Synchronous
b
DQ
c
DQ
d
M
M
Read Protocol Mode
1,
2
Pins
ZZ
Input-
Asynchronous
ZQ
Input
V
Power Supply
DD
V
I/O Power Supply
DDQ
V
Input-
REF
Reference Voltage
V
Ground
SS
TDO
JTAG serial output
Synchronous
TDI
JTAG serial input
Synchronous
TMS
Test Mode Select
Synchronous
TCK
JTAG serial clock
NC
–
Document No: 001-07844 Rev. *A
PRELIMINARY
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the K.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
BWS
controls DQ
, BWS
controls DQ
c
c
d
Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to initiate a write sequence and high to initiate a read sequence.
Clock Inputs. Used to capture all synchronous inputs to the device.
Chip Enable Input, active LOW. Sampled on the rising edge of CLK. Used to
select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a tri-state condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE. DQ a,b,c,d are 9 bits wide
Mode control pins, used to set the proper read protocol. For specified device
operation, M
must be connected to V
1
These mode pins must be set at power-up and cannot be changed during device
operation.
ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep"
condition with data integrity preserved.
Output Impedance Matching Input. This input is used to tune the device outputs to
the system data bus impedance. Q
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
, which enables the minimum impedance mode. This pin
DDQ
cannot be connected directly to GND or left unconnected.
Power supply inputs to the core of the device. For this device, the V
Power supply for the I/O circuitry. For this device, the V
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Ground for the device. Should be connected to ground of the system.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
Serial clock to the JTAG circuit.
No connects.
CY7C1330AV25
CY7C1332AV25
Description
controls DQ
a
.
d
during the previous clock rise of the read cycle. The
[x:0]
, and M
must be connected to V
SS
2
output impedance are set to 0.2 x RQ, where
[x:0]
DDQ
, BWS
controls DQ
,
a
b
b
–DQ
are placed in
a
d
or V
.
DD
DDQ
is 2.5V.
DD
is 1.5V.
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