Cypress Semiconductor CY7C1364C Lembar Spesifikasi - Halaman 14
Jelajahi secara online atau unduh pdf Lembar Spesifikasi untuk Perangkat Keras Komputer Cypress Semiconductor CY7C1364C. Cypress Semiconductor CY7C1364C 19 halaman. 9-mbit (256k x 32) pipelined sync sram
Halaman CetakSwitching Waveforms
Read/Write Cycle Timing
CLK
t CH
t ADS
t ADH
ADSP
ADSC
t AS
t AH
ADDRESS
A1
A2
BWE,
BW[A:D]
t CES
t CEH
CE
ADV
OE
Data In (D)
High-Z
Data Out (Q)
High-Z
Back-to-Back READs
Notes:
20. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
21. GW is HIGH.
Document #: 38-05689 Rev. *E
(continued)
[18,20, 21]
t CYC
t CL
A3
t WES
t WEH
t DS
t DH
t CO
D(A3)
t OEHZ
t CLZ
Q(A1)
Q(A2)
Single WRITE
A4
t OELZ
Q(A4)
Q(A4+1)
BURST READ
DON'T CARE
UNDEFINED
CY7C1364C
A5
A6
D(A5)
D(A6)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Page 14 of 18
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