Cypress Semiconductor CY7C1365C Lembar Spesifikasi - Halaman 8

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Halaman Cetak
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ Active to Sleep current
ZZI
t
ZZ Inactive to exit Sleep current
RZZI
[3, 4, 5, 6, 7]

Truth Table

Cycle Description
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
3. X = "Don't Care." H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals (BW
(BW
, BW
, BW
, BW
), BWE, GW = H.
A
B
C
D
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05690 Rev. *E
Description
Address
Used
CE
CE
CE
1
3
2
None
H
X
X
None
L
X
L
None
L
H
X
None
L
X
L
None
X
X
X
None
X
X
X
External
L
L
H
External
L
L
H
External
L
L
H
External
L
L
H
External
L
L
H
Next
X
X
X
Next
X
X
X
Next
H
X
X
Next
H
X
X
Next
X
X
X
Next
H
X
X
Current
X
X
X
Current
X
X
X
Current
H
X
X
Current
H
X
X
Current
X
X
X
Current
H
X
X
, BW
, BW
A
B
Test Conditions
ZZ > V
– 0.2V
DD
ZZ > V
– 0.2V
DD
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ZZ
ADSP
ADSC
ADV WRITE
L
X
L
X
L
L
X
X
L
L
X
X
L
H
L
X
L
H
L
X
H
X
X
X
L
L
X
X
L
L
X
X
L
H
L
X
L
H
L
X
L
H
L
X
L
H
H
L
L
H
H
L
L
X
H
L
L
X
H
L
L
H
H
L
L
X
H
L
L
H
H
H
L
H
H
H
L
X
H
H
L
X
H
H
L
H
H
H
L
X
H
H
, BW
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
C
D
. Writes may occur only on subsequent clocks
[A: D]
CY7C1365C
Min.
Max.
Unit
50
mA
2t
ns
CYC
2t
ns
CYC
2t
ns
CYC
0
ns
OE
CLK
DQ
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
X
Tri-State
X
L
L-H
Q
X
H
L-H
Tri-State
L
X
L-H
D
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
L
X
L-H
D
L
X
L-H
D
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
L
X
L-H
D
L
X
L-H
D
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