Cypress Semiconductor STK14C88-3 Lembar Spesifikasi - Halaman 12

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Halaman Cetak
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Parameter
Alt
[16]
t
t
RC
AVAV
[18, 19]
t
t
SA
AVEL
[18, 19]
t
t
CW
ELEH
[18, 19]
t
t
HACE
ELAX
t
RECALL
Switching Waveforms
ADDRESS
t
SA
CE
OE
DQ (DATA)
Notes
18. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).
19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-50592 Rev. **
[18, 19]
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Figure 12. CE Controlled Software STORE/RECALL Cycle
t
RC
A
D
D
R
E
S
S
#
1
t
SCE
t
HACE
DATA VALID
35 ns
Min
Max
35
0
25
20
20
[19]
t
RC
A
D
D
R
E
S
S
#
6
t
/ t
STORE
RECALL
HIGH IMPEDANCE
DATA VALID
STK14C88-3
45 ns
Unit
Min
Max
45
ns
0
ns
30
ns
20
ns
μs
20
Page 12 of 17
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