Cypress Semiconductor Z9973 Lembar Spesifikasi - Halaman 6
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Halaman Cetak[3]
Maximum Ratings
Maximum Input Voltage Relative to V
Maximum Input Voltage Relative to V
Storage Temperature: ................................–65 C to + 150 C
Operating Temperature: ................................ –40 C to +85 C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:
DC Parameters
(V
= 2.9V to 3.6V, V
DD
Parameter
Description
V
Input LOW Voltage
IL
V
Input HIGH Voltage
IH
V
Peak-to-Peak Input Voltage
PP
PECL_CLK
V
Common Mode Range PECL_CLK
CMR
I
Input Low Current
IL
I
Input High Current
IH
V
Output Low Voltage
OL
V
Output High Voltage
OH
I
Quiescent Supply Current
DDQ
I
PLL Supply Current
DDA
I
Dynamic Supply Current
DD
C
Input Pin Capacitance
IN
AC Parameters
(V
= 2.9V to 3.6V, V
DD
Parameter
Tr / Tf
TCLK Input Rise / Fall
Fref
Reference Input Frequency
FrefDC
Reference Input Duty Cycle
Fvco
PLL VCO Lock Range
Tlock
Maximum PLL Lock Time
Tr / Tf
Output Clocks Rise/Fall Time
Notes:
3.
The voltage on any input or I/O pic cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4.
Parameters are guaranteed by design and characterization. Not 100% tested in production.
5.
Maximum and minimum input reference is limited by VC0 lock range.
6.
Outputs loaded with 30 pF each.
Document #: 38-07089 Rev. *D
: ............ V
– 0.3V
SS
SS
: ............. V
+ 0.3V
DD
DD
20 mA
= 3.3V ±10%, T
DDC
[9]
[10]
[10]
[11]
I
= 20 mA
OL
[11]
I
= –20 mA
OH
V
only
DD
QA and QB @ 60 MHz,
QC @ 120 MHz, C
QA and QB @ 25 MHz,
QC @ 50 MHz, C
= 3.3V ±10%, T
DDC
Description
[6]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
the range:
V
< (V
or V
) < V
SS
IN
OUT
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
or V
SS
= –40 C to +85 C)
A
Conditions
V
DD
= 30 pF
L
= 30 pF
L
[4]
= –40 C to +85 C)
A
Conditions
Note 5
0.8V to 2.0V
Z9973
and V
should be constrained to
OUT
.
).
DD
Min.
Typ.
Max.
Unit
V
0.8
SS
2.0
V
DD
300
1000
– 2.0
V
– 0.6
DD
–120
120
0.5
2.4
10
15
15
20
225
125
4
Min.
Typ.
Max.
Units
3.0
Note 5
MHz
25
75
200
480
MHz
10
0.15
1.2
Page 6 of 9
V
V
mV
V
µA
µA
V
V
mA
mA
mA
pF
ns
%
ms
ns
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