EG&G ORTEC 552 Panduan Pengoperasian dan Servis - Halaman 12

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For the external bias circuit, a dc level between 0 and

-10 V can be furnished through CN2and is divided by R56

and R57. The result that is selected by switch S2 is then

furnished through the same buffering and coupling net

work to the lower-level discriminator.

5.4.

UPPER-LEVEL BIAS

The threshold for the upper-level discriminator is ad

justed with the front panel Upper-Level control, R48. The

range for this control is 0 to -5 V. The adjusted level is

buffered through IC1-14 and furnished through either

R60 or R61, through operational amplifier IC1-8, and to

the noninverting input of the upper-level discriminator,

IC2. When switch S3 is set at either Integral or Normal,

the gain of this adjusted bias is 1.0; when the switch

selects Window, the gain is reduced to 0.1 and the effec

tive range of the control is thus reduced by a factor of 10.

Also, when the switch selects Window, the level that is

furnished from IC1-1 for the lower-level discriminator

is also furnished through R62 to IC1-8. Thus the adjusted

lower level becomes, effectively, the base to which the

upper level is added and the result is a window of 0 to 1 V

based on the lower-level threshold.

5.5.

INPUT CIRCUIT

The analog input signal to be analyzed is furnished

through CN1 on the front panel and through an attenuator

network. The ATTN switch, SI, on the front panel can be

set at XI, X10, or X100. When it is set at XI, the full am

plitude input signal is furnished to a peak stretcher and

through a divide-by-two network into each of the four

discriminator circuits. The output of the peak stretcher

is divided by two so that the original input amplitude

range of 0 to 10 V corresponds to a 0 to 5 V range at the

input to each discriminator and this corresponds directly

to the 0 to 5 V range that is provided for each comparator.

If the switch is set at X10 attenuation, the input signal is

divided through R1 and R5 so that 1/10 of the input signal

amplitude is available for the internal circuits. If the switch

is set at X100, the signal is attenuated to 1% of its original

amplitude by division through R1 in series with the par

allel network of R5 and R3.

The attenuator output is applied to a stretcher circuit that

stores the peak amplitude of its input as a stretched level

until it is discharged. The discharge signal is furnished

from 106-12 and occurs only after a trigger has occurred

in both the channel A and channel B discriminator out

puts and the lower-level discriminator has been reset.

Because of this logic, if the channel B-Fraction selector

switch on the front panel is set at Bl and the input does

not cross zero, the channel B discriminator will not be

triggered and the module will lock up since its logic can

not be reset.

Jumper J1, shown on the schematic, is installed during a

test adjustment of the dc zero level of the stretcher and

is removed for normal operation. See Section 6.2 for cali

bration information.

5.6. LOWER-LEVEL DISCRIMINATOR

Integrated circuit package IC3 is the lower-level discrim

inator. As long as the input level at its pin 4 is lower than

the reference level at pin 3, the output at pin 9 is high.

When the input amplitude rises through the reference

level, the output at pin 9 switches to the low state. Then

when the input amplitude decays back through the refer

ence level, the pin 9 output switches back to high again.

When the pin 9 output goes low, this sets flip flop IC4-6

and IC4-3 high to identify the lower-level trigger point.

The switch to high at IC4-3 is furnished through an output

generator, Q18 through Q22, to generate a NIM-standard

slow positive pulse through LL Out connector CN6. It is

also furnished as one input to 105-11, where a decision is

made for the single-channel logic. With both inputs high,

105-11 switches to low to identify that the logic is satis

fied. Unless this condition is cancelled by a response from

the upper-level discriminator before the constant-fraction

circuits are triggered, the output of 103-11 enables the

gates for the SCA outputs.

To prevent multiple firings of the discriminator near the

threshold level, a hysteresis of about 5 mV is furnished

to the lower-level discriminator by R220 and R219.

5.7.

UPPER-LEVEL DISCRIMINATOR

Integrated circuit package 102 is the upper-level discrimi

nator. As long as the input level at its pin 4 is lower than

the reference level at pin 3, the output at pin 9 is high.

When the input amplitude rises through the reference

level, the output at pin 9 switches to low and sets flip flop

104-11 and 104-8, with 104-11 going high. If switch S3

is set at Normal or Window, the upper-level discriminator

response provides a low from 105-8 to cancel the logic at

105-11 and to prevent any SCA output from being gener

ated. If switch S3 is set at Integral, the upper-level re

sponse is not used at 103-11.

When 104-11 goes high, an output generator, 013

through 017, triggers and generates a NIM-standard slow

positive pulse through UL Out connector 0N4.

A 5 mV hysteresis is used to prevent multiple firings near

the threshold for 102. This is generated by R218and R124.

5.8. CHANNEL A DISCRIMINATOR

The channel A discriminator is 107. The input signal is

furnished through pin 3 and the reference level is fur

nished through pin 4. At the onset of the input pulse, the

level at pin 3 rises faster than the level through pin 4 and

this generates a low output at pin 9 and a high at pin 11.

The level at pin 4 is furnished from the peak stretcher so

it will remain at a fixed level, which is a proportional

amplitude with reference to the input peak, while the input

pulse decays. When the input pulse decay crosses the

reference level, 107 is reset to generate the channel A

trigger. Jumper J3 on the printed circuit board selects

which of the three fractions is effective for the reference

level; this can be set at 10%, 20%, or 50% down from the

peak amplitude (90%, 80%, or 50% respectively of the

peak amplitude).

When 107 is reset and its pin 11 goes to ground, a 10-ns

negative pulse is generated from 108-15 through Q23,

108-6, and DL1. If the A SOA gate, 108-2, has been en

abled by a low from Q27A (logic is satisfied) the output