ComBlock COM-1826 Manuale - Pagina 13

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Digital Test Points

The digital test points below are only available

when no ADCs/DACs are installed.

Test PointDefinition

UDP/TCP input data activity.

SDDS receive data valid flag from UDP or TCP.

(8ns per input byte)

SDDS input buffer underflow condition. '1'

when the sender is not fast enough.

Recovered carrier/center frequency (coarse)

Carrier lock

Code lock

Signal present

Recovered chip clock

Recovered I-channel symbol clock

I-code start

A10

I-code replica

A11

I-channel before despreading (compare with

code replica)

A12

Demodulated bit (I)

A13

Demodulated bit (Q)

A14

BER tester synchronized (I or Q depending on

REG27(3))

A15

Byte error detected by BER tester (I

or Q depending on REG27(3))

A16

Viterbi decoder (I) synchronized (pulse every 1K

bits)

A17

Viterbi decoder (Q) synchronized (pulse every

1K bits)

A19

Periodic pulses every 2047 bits when receiving a

PRBS-11 test sequence

Operation

Monitoring & Control

M&C is possible over USB and LAN/TCP.

A pre-requisite for using USB is the prior

installation of the ComBlock USB driver.

Monitoring and control is through the USB and

LAN xA connectors on the back panel.

At manufacturing, the default M&C LAN address is

172.16.1.2. It can be subsequently changed via USB

or LAN/TCP.

The LAN xA connector is also shared with TCP

connections for modulator inputs and dynamic

profiles inputs.

SDDS input stream

The LAN xB connectors on the back panel are

reserved for SDDS-formatted input streams.

The input stream can be received on UDP port

29495 or TCP-IP port 1028. Control register

REG0(0) selects UDP versus TCP.

The static IP address is defined in control registers

REG37-40.

Note: It is important to ensure that the data source is

fast enough to send 200 Mbits/s of UDP or TCP

data with latency less than 2.5ms (the receiver input

elastic buffer depth). When in doubt, please check

the test point A2 with an oscilloscope.