DAQ DVI-CL01 Manuale d'uso - Pagina 6

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In Medium Mode, even pixels are output from the left Single Output Connector (J2) of [Figure 2-1]
and odd pixels are output from the remaining right connector (J3), and the pixel clock frequency is
half of that of Base mode.
(See Table 2.)
[Table 2. Two pixel per Clock Mode Data Mapping]
DATA
BLUE[7..0] – Odd
GREEN[7..0] - Odd
RED[7..0] - Odd
BLUE[7..0] – Even
GREEN[7..0] - Even
RED[7..0] - Even
(4) RS232 communication is possible through the Serial communication (SerTFG/SerTC) part of Cameral
Link and the Dusb9 pin connector.
Two Pixel per Clock Output
18bpp
QE[7..0]
QE[15..10]
QE[23..18]
QO[7..0]
QO[15..10]
QO[23..18]
DVI-CL01 User's Manual
26bpp
QE[7..0]
QE[15..8]
QE[23..16]
QO[7..0]
QO[15..8]
QO[23..16]
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