Dynamic Engineering PCIe8LXMCX2 Manuale d'uso - Pagina 15
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Stampa la paginaSpecifications
Logic Interfaces:
Access types:
CLK rates supported:
Software Interface:
Initialization:
Interface:
Dimensions:
Construction:
PCIe up to 8 lanes per XMC Gen1 and Gen2 compliant switch and
clock buffer.
PCIe TLP transactions. MSI interrupts.
Gen1 and Gen2
switch is auto configured and usually will not require any user
intervention.
switch selections for VPWR, bezel grounding, and cable options
XMC front bezel via PCIe bracket and User IO connector via DIN or
SCSI connector
full length PCIe board with offset PCI card guide support.
High Temp FR4 Multi-Layer Printed Circuit, Through Hole and
Surface Mount Components.
Embedded Solutions
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