Avnet UltraZed Series Schema di cablaggio - Pagina 4

Sfoglia online o scarica il pdf Schema di cablaggio per Sistemi I/O Avnet UltraZed Series. Avnet UltraZed Series 18. I/o carrier card

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1
A
+VCCO_1V8
Vddd
R1
2
FB1
C1
C2
C3
10uF
0.1uF
0.1uF
GND
USER NOTE:
SEL [0:1] Mode (default):
JP1 installed, J1/J2 installed from
pins 1-2. This set's mode 3.
I2C Mode: JP1 not installed, J1/J2
installed
B
on pins 1-2.
C
9[5D]
JX2_HP_DP_29_N
9[5D]
JX2_HP_DP_29_P
9[4D]
JX2_HP_SE_04
+VCCO_1V8
D
1
2
CLOCK SYNTHESIZER & LVDS PORT
Vdda
C4
C5
1uF
0.1uF
GND
J1
5-146280-3
10[2B], 5[6C]
CC_SDA
10[3B], 5[6C]
CC_SCL
J2
5-146280-3
Layout Note:
50 ohm single ohm.
100 ohm +/- 10% diff routing.
+3.3V
C6
+VCCO_1V8
0.1uF
R7
C7
U2
4.75K
0.1uF
1
14
VCCA
VCCB
(TP_SCL)
2
13
A1
B1
(TP_SDA)
3
12
A2
B2
(TP_IRQ_N)
4
11
A3
B3
5
10
A4
B4
R10
8
OE
4.75K
6
NC
9
7
NC
GND
TXS0104EPWR
2
3
4
IDT CLOCK SYNTHESIZER
Vddd
U1
1
CLKIN
+VCCO_1V8
2
CLKINB
R2
10.00K
8
SEL1/SDA
9
SEL0/SCL
24
OUT0_SELB_I2C
R3
R4
10.00K
10.00K
7
SD/OE
6
CLKSEL
5-146280-2
+VCCO_1V8
JP1
R5
R6
10.00K
10.00K
GND
LVDS CONNECTOR
(TP_D0_P)
9[4C]
JX2_HP_DP_24_P
(TP_D0_N)
9[4C]
JX2_HP_DP_24_N
(TP_D1_P)
9[5C]
JX2_HP_DP_25_P
(TP_D1_N)
9[5C]
JX2_HP_DP_25_N
(TP_D2_P)
9[4C]
JX2_HP_DP_26_GC_P
(TP_D2_N)
9[4D]
JX2_HP_DP_26_GC_N
R8
R9
(TP_D3_P)
9[5C]
JX2_HP_DP_27_GC_P
4.75K
4.75K
(TP_D3_N)
9[5C]
JX2_HP_DP_27_GC_N
TP_SCL
TP_SDA
(TP_CLK_P)
9[4D]
JX2_HP_DP_28_P
(TP_CLK_N)
9[4D]
JX2_HP_DP_28_N
TP_IRQ_N
R11
+3.3V
0
1
+VCCO_1V8
DNP
D1
BAT400D-7-F
3
4
5
Vdda
Vddd
Layout Note:
Differential pairs:
Route at 100 ohms
Termination on JX3
connectors.
20
(USB3_P)
OUT1
GTR_REFCLK0_P
19
(USB3_N)
OUT1B
GTR_REFCLK0_N
17
(SATA_P)
OUT2
GTR_REFCLK1_P
16
(SATA_N)
OUT2B
GTR_REFCLK1_N
14
(DPORT_P)
OUT3
GTR_REFCLK3_P
13
(DPORT_N)
OUT3B
GTR_REFCLK3_N
11
(PL_SYSCLK_P)
OUT4
JX1_HP_DP_36_GC_P
12
(PL_SYSCLK_N)
OUT4B
JX1_HP_DP_36_GC_N
EPAD
5P49V5935B521LTGI
25
ADDR: 0xD4 - Default
ADDR: 0xD0 - Alternate
GND
P1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21
17
SH
22
18
SH
23
19
SH
24
20
SH
3
R12
0
Project Name:
UltraZed IO Carrier Card
C8
0.1uF
Doc Num:
SCH-US1CAR
SH_GND4
Sheet Title:
04 - Clock & LVDS Port.SchDoc
5
6
A
10[3B]
}
MODE 3: 52 MHz
10[3B]
10[2B]
}
MODE 3: 125 MHz
10[2B]
10[2B]
}
MODE 3: 27 MHz
10[2B]
9[1C]
}
MODE 3: 300 MHz
9[1C]
B
C
SH1
SH2
SH3
D
Avnet Engineering Services
PCB Rev:
BOM:
Variant:
1
01
02
Date:
Time:
11/9/2016
1:51:52 PM
Size:
Sheet:
B
4
17
of
6