Dell N1548P Istruzioni per l'aggiornamento del firmware - Pagina 7
Sfoglia online o scarica il pdf Istruzioni per l'aggiornamento del firmware per Interruttore Dell N1548P. Dell N1548P 17. Emcnetworking switches
- 1. Table of Contents
- 2. Introduction
- 3. Global Support
- 4. Firmware Upgrade Overview
- 5. Firmware Downgrade Overview
- 6. How to Access Serial Console on Dell EMC Networking N1500 Series Switches
- 7. Upgrade Example of Dell EMC Networking N1500 Series Switches
- 8. Upgrade Stack of Dell EMC Networking N1500 Series Switches
- 9. Switch Recovery Procedure
- 10. Switch Recovery Example
- 11. End of Document
Upgrade Dell EMC Networking N1500 Series Switches
6. Reload the switch.
console#reload
Management switch has unsaved changes.
Are you sure you want to continue? (y/n) y
Configuration Not Saved!
Are you sure you want to reload the stack? (y/n) y
NOTE:
Using the serial port to update firmware, following output will be
observed. If logged in via telnet or SSH, rebooting switch will close the
connection. Rebooting may take several minutes to complete and the switch
may reboot itself more than once during the upgrade procedure.
Reference platform resetting ...
starting pid 17Rebooting system!
The system is going down NOW!
Sent SIGTERM to all processes
Sent SIGKILL to all processes
Requesting system reboot
U-Boot 2012.10-00244-g9552470cd8 (Feb 20 2018 - 15:54:29)
I2C:
ready
BENCH SCREENING TEST1
=========================================
IPROC_XGPLL_CTRL_3: 0x05400000
IPROC_XGPLL_STATUS: 0x80000490
DCO code: 73
=========================================
DEV ID = 0xdb56
SKU ID = 0xb150
DDR type: DDR3
MEMC 0 DDR speed = 667MHz
PHY revision version: 0x00024006
ddr_init2: Calling soc_ddr40_set_shmoo_dram_config
ddr_init2: Calling soc_ddr40_phy_calibrate
C01. Check Power Up Reset_Bar
C02. Config and Release PLL from reset
C03. Poll PLL Lock
C04. Calibrate ZQ (ddr40_phy_calib_zq)
C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT
C06. DDR40_PHY_DDR3_MISC
C07. VDL Calibration
C07.1
C07.2
C07.4
C07.4.1
C07.4.4
VDL calibration result: 0x30000003 (cal_steps = 0)
C07.4.5
C07.4.6
C07.5
C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....
C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....
C10. Wait for Phy ReadyDone.
DDR phy calibration passed
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