Dialog Semiconductor SLG46824 Manuale di programmazione - Pagina 4

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ISPG-SLG46824/6
SLG46824/6
2
Table 1: I
C Specifications
Symbol
Parameter
F
Clock Frequency, SCL
SCL
t
Clock Pulse Width Low
LOW
t
Clock Pulse Width High
HIGH
Input Filter Spike Suppression
t
I
(SCL, SDA)
t
Clock Low to Data Out Valid
AA
Bus Free Time between Stop
t
BUF
and Start
t
Start Hold Time
HD_STA
t
Start Set-up Time
SU_STA
t
Data Hold Time
HD_DAT
t
Data Set-up Time
SU_DAT
t
Inputs Rise Time
R
t
Inputs Fall Time
F
t
Stop Set-up Time
SU_STD
t
Data Out Hold Time
DH
IO14
1
20
IO13
2
19
IO12
3
18
IO11
4
17
IO10
5
16
IO9
6
15
V
7
14
DD2
IO8
8
13
IO7
9
12
GND
10
11
Figure 2: TSSOP-20 Pin Configuration
Condition
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
V
= 2.3 V to 5.5 V
DD
Revision 1.1
4 of 15
V
DD
IO0
IO1
IO2
IO3
IO4
IO5
SCL
SDA
IO6
Fast-Mode
Fast-Mode Plus
Min
Typ
Max
Min
--
--
400
--
1300
--
--
500
600
--
--
260
--
--
50
--
--
--
900
--
1300
--
--
500
600
--
--
260
600
--
--
260
0
--
--
0
100
--
--
50
--
--
300
--
--
--
300
--
600
--
--
260
50
--
--
50
© 2019 Dialog Semiconductor
Unit
Typ
Max
--
1000 kHz
--
--
ns
--
--
ns
--
50
ns
--
450
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
120
ns
--
120
ns
--
--
ns
--
--
ns
4-Mar-2019