CIRCUIT DESIGN STD-302N-R Manuale operativo - Pagina 5

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Receiver part
Item
Receiver type
1st IF frequency
2nd IF frequency
Maximum input level
BER (0 error/2556 bits)
*2
BER (1 % error)
Sensitivity 12dB/ SINAD
Spurious response rejections
Adjacent CH selectivity
Blocking
*4
Intermodulation
DO output level
RSSI rising time
Time until valid Data-out
st
Spurious radiation (1
RSSI
Notice
Communication range depends on the operation environment and ambient surrounding
Specifications are subject to change to improve the characteristics and for other reasons.
The time required until a stable DO is established may get longer due to the possible frequency drift
caused by operation environment changes, especially when switching from TX to RX, from RX to TX and
changing channels. Please make sure to optimize the timing. The recommended preamble is more than
20 ms.
Antenna connection is designed as pin connection. RF output power, sensitivity, spurious emission and
spurious radiation levels may vary with the pattern used between the RF pin and the coaxial connection.
Please make sure to verify those parameters before use.
The feet of the shield case should be soldered to the wide GND pattern to avoid any change in
characteristics.
Notes about the specification values
*1 BER: RF level where no error per 2556 bits is confirmed with the signal of PN9 and 4800 bps.
*2 BER (1 % error): RF level where 1% error per 2556 bits is confirmed with the signal of PN9 and 4800 bps.
*3 Spurious response, CH selectivity, Blocking: Jamming signal used in the measurement is unmodulated.
*4 Intermodulation: Ratio between the receiver input level with BER 1% and the signal level (PN9 4800 bps)
added at the points of 'Receiving frequency - 200 kHz ' + ' Receiving frequency -100kHz' with which BER 1%
is achieved.
*5 Time until valid Data-out: Valid DO is determined at the point where Bit Error Rate meter starts detecting
the signal of 4800 bps, 1010 repeated signal.
All specifications are specified based on the data measured in a shield room using the PLL setting controller
board prepared by Circuit Design.
Measuring equipment:
SG=ANRITSU communication analyzer MT2605
Spectrum analyzer = ANRITSU MS2663G / BER measure = ANRITSU MP1201G
OG_STD-302N-R335M_v10e
MIN
Double superheterodyne
MHz
kHz
dBm
*1
dBm
-108
dBm
dBm
*3
dB
*3
dB
dB
dB
V
ms
*5
ms
Lo)
dBm
300
mV
190
TYP
MAX
21.7
450
10
-117
-120
-120
70
55
50
84
50
0
2.8
30
50
50
100
50
70
70
120
-57
360
420
250
310
Specifications are subject to change without prior notice
5
OPERATION GUIDE
Remarks
PN 9 4800 bps
PN 9 4800 bps
fm1 k/ dev 2 kHz CCITT
1 st Mix, 2 signal method, 1 % error
2 nd Mix, 2 signal method, 1 % error
+/- 25 kHz, 2 signal method, 1 % error
Jamming signal +/- 1MHz,
2 signal method, 1% error
2 signal method, 1 % error
L = GND H = 2.8 V
CH shift of 25 kHz (from PLL setup)
When power ON (from PLL setup)
CH shift of 25 kHz (from PLL setup)
When power ON (from PLL setup)
Conducted 50 Ω
With -97 dBm at 335.7875 MHz
With -113 dBm at 335.7875 MHz
Circuit Design, Inc.