CIRCUIT DESIGN STD-302N-R Manuale operativo - Pagina 11

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How to calculate the setting values for the PLL register

The PLL IC manual shows that the PLL frequency setting value is obtained with the following equation.
f
= [(M x N)+A] x f
vco
osc
f
: Output frequency of external VCO
vco
M: Preset divide ratio of the prescaler (64 or 128)
N: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127 A<N))
f
: Output frequency of the reference frequency oscillator
osc
R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
With STD-302N-R, there is an offset frequency (f
Therefore the expected value of the frequency generated at VCO (f
f
= f
= f
– f
vco
expect
ch
offset
The PLL internal circuit compares the phase to the oscillation frequency f
frequency (f
) must be decided. f
comp
frequency oscillator by reference counter R. STD-302N-R uses 21.25 MHz for the reference clock f
one of 6.25 kHz, 12.5 kHz or 25 kHz.
The above equation 1 results in the following with n = M x N + A, where "n" is the number for division.
f
=n*f
---- Equation 3
vco
comp
Also, this PLL IC operates with the following R, N, A and M relational expressions.
R=f
/f
---- Equation 5
osc
comp
As an example, the setting value of RF channel frequency f
The constant values depend on the electronic circuits of STD-302N-R.
Conditions:
The frequency of VCO will be
f
= f
= f
- f
vco
expect
ch
offset
Dividing value "n" is derived from Equation 4
n = f
/ f
= 848.025MHz/25kHz = 33921
vco
comp
Value "R" of the reference counter is derived from Equation 5.
R = f
/f
= 21.25MHz/25kHz = 850
osc
comp
Value "N" of the programmable counter is derived from Equation 6.
N = INT (n/M) = INT(33921/64) = 530
Value "A" of the swallow counter is derived from Equation 7.
A = n – (M x N) = 33921 – 64 x 530 = 1
The frequency of STD-302N-R is locked at a center frequency f
R obtained with the above equations as serial data. The above calculations are the same for the other
frequencies.
Excel sheets that contain automatic calculations for the above equations can be found on our web site
(www.cdt21.com/).
The result of the calculations is arranged as a table in the CPU ROM. The table is read by the channel
change routine each time the channel is changed, and the data is sent to the PLL.
OG_STD-302N-R-458M_v12e
/ R
-- Equation 1
Equation 2
----
is made by dividing the frequency input to the PLL from the reference
comp
n = f
/f
vco
comp
N = INT (n / M) ---- Equation 6
INT: integer portion of a division.
Channel center frequency:
Constant: Offset frequency:
Constant: Reference frequency:
Set 25 kHz for Phase comparison frequency and 64 for Prescaler value M
= 869.725 –21.7 = 848.025MHz
) 21.7 MHz for the transmission RF channel frequency f
offset
expect
---- Equation 4
note: f
A = n - (M x N) ---- Equation 7
869.725 MHz can be calculated as below.
ch
f
= 869.725 MHz
ch
f
offset
f
=21.25 MHz
osc
by inputting the PLL setting values N, A and
ch
11
OPERATION GUIDE
) is as below.
This phase comparison
vco.
= f
/R
comp
osc
=21.7 MHz
Circuit Design, Inc.
.
.
ch
f
is
osc.
comp