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Atlys Reference Manual

EDK designs can use the xps_tft IP core (and its associated driver) to access the HDMI ports. The

xps_tft core reads video data from the DDR2 memory, and sends it to the HDMI port for display on an

external monitor. The IP core is capable of 1080P resolution at 24 bits per pixel.

An EDK reference design available on the Digilent website (and included as a part of the User Demo)

displays a bitmap file on an HDMI-connected monitor. Another second EDK reference design

(included in the User test available though Adept) displays a gradient color bar and a text in the center

of the screen.

Audio (AC-97)

The Atlys board includes a National

Semiconductor LM4550 AC '97 audio

codec (IC19) with four 1/8" audio

jacks for line-out (J16), headphone-

out (J18), line-in (J15), and

microphone-in (J17). Audio data at

up to 18 bits and 48KHz sampling is

supported, and the audio in (record)

and audio out (playback) sampling rates can be different. The microphone jack is mono, all other

jacks are stereo. The headphone jack is driven by the audio codec's internal 50mW amplifier. The

table below summarizes the audio signals.

The LM4550 audio codec is compliant to the AC '97 v2.1 (Intel) standard and is connected as a

Primary Codec (ID1 = 0, ID0 = 0). The table below shows the AC '97 codec control and data signals.

All signals are LVCMOS33.

Signal Name FPGA Pin Pin Function

AUD-BIT-CLK AH17

AUD-SDI

AE18

AUD-SDO

AG20

AUD-SYNC

Doc: 502-178

12.288MHZ serial clock output, driven at one-half the frequency of the

24.576MHz crystal input (XTL_IN).

Serial Data In (to the FPGA) from the codec. SDI data consists of AC

'97 Link Input frames that contain both configuration and PCM audio

data. SDI data is driven on the rising edge of AUD-BIT-CLK.

Serial Data Out (to the codec) from the FPGA. SDO data consists of AC

'97 Link Output frames that contain both configuration and DAC audio

data. SDO is sampled by the LM4550 on the falling edge of AUD-BIT-

CLK.

AC Link frame marker and Warm Reset. SYNC (input to the codec)

defines AC Link frame boundaries. Each frame lasts 256 periods of

AUD-BIT-CLK. SYNC is normally a 48kHz positive pulse with a duty

cycle of 6.25% (16/256). SYNC is sampled on the rising edge of AUD-

BIT-CLK, and the codec takes the first positive sample of SYNC as

defining the start of a new AC Link frame. If a subsequent SYNC pulse

occurs within 255 AUD-BIT-CLK periods of the frame start it will be

ignored. SYNC is also used as an active high input to perform an

(asynchronous) Warm Reset. Warm Reset is used to clear a power-

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