Digilent Atlys Manuale di riferimento - Pagina 17

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Atlys Reference Manual

Expansion Connectors

The Atlys board has a 68-pin VHDC connector for high-speed/parallel I/O, and an 8-pin Pmod

connector for lower speed and lower pin-count I/O.

The VHDC connector includes 40 data signals (routed as 20 impedance-controlled matched pairs), 20

grounds (one per pair), and eight power signals. This connector, commonly used for SCSI-3

applications, can accommodate data rates of several hundred megahertz on every pin. Both board-to-

board and board-to-cable mating connectors are available. Data sheets for the VHDC connector and

for mating board and cable connectors can be found on the Digilent website, as well as on other

vendor and distributor websites. Mating connectors and cables of various lengths are also available

from Digilent and from distributors.

All FPGA pins routed to the VHDC connector are located in FPGA I/O bank 2. The bank 2 I/O power

supply pins and the VHDC connector's four Vcc pins are connected to an exclusive sub-plane in the

PCB, and this sub-plane can be connected to 2.5V or 3.3V, depending on the position of jumper

JP12. This arrangement allows peripheral boards and the FPGA to share the same Vcc and signaling

voltage across the connector, whether it be 3.3V or 2.5V.

The unregulated board voltage Vswt

(nominally 5V) is also routed to four other

VHDC pins, supplying up to 1A of additional

current to peripheral boards.

All I/O's to the VHDC connector are routed

as matched pairs to support LVDS signaling,

commonly powered at 2.5V. The connector

uses a symmetrical pinout (as reflected

around the connector's vertical axis) so that

peripheral boards as well as other system

boards can be connected. Connector pins 15

and 49 are routed to FPGA clock input pins.

Doc: 502-178

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