Epson LQ-570+ Manuale di servizio - Pagina 27

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2.3.6 Printhead Drive Circuit

Figure 2-24 shows the printhead drive circuit block diagram. The print data already is expanded to

create the image data. The CPU splits up this data three times and transfers this information to the

latch circuit within the Head Gate Array(lC2). The CPU samples the voltage of the +35 V line via the

length of this pulse corresponds to the voftage of the +35 V line. This pulse becomes the head drive

signal. In this way, Head Gate Array(iC2) outputs head drive signals (signals HD1 to HD24) that relate

to voltage level through the width of the pulses. These signals are output to the head for each of the

section of print data that were created by subdividing the data three times before sending.

By sampling the +35 V line voltage and determining the length of the head drive signal, it is possible

to maintain the energy supplied to the head at a mnstant level. If the voltage of the +35 V line is .

HIGH, the CPU shortens the output pulse. If the voftage of the +35 V line is LOW, the CPU lengthen

the output pulse.

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Figure 2-24. Printhead Drive Circuit

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2-19

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