Toshiba TLP-710U Manuale di formazione tecnica - Pagina 26
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7-7. Automatic Adjustment,
Timing Generation Circuits
The automatic adjustment circuit consists of an
EPF6024AQC208 (QD014) and the sub-microprocessor
(QL500).
A sync signal supplied is directly entered QD014 in
addition to the sync signal used for the PLL. By testing
polarity, frequency, and line number of these signals, a
type of the input signal is identified and the best operat-
ing conditions are set. If the type of the input signal is
not identified, video effective period, etc. are determined
by testing the video signal entered and the best operating
conditions are set. A G signal is used as the video signal
and branched after the selector (QD801), and entered
from the identification A/D converter (QD013) in passing
through exactly the same circuit as that for the display
s i g n a l .
QD014 generates various timing signals for OSD,
clamping, IP00C702, LCD DRIVER etc.
The QD014 is a PLD (Programmable Logic Device).
The contents of the IC are written on the ROM (QD016)
for PLD, and they are automatically read into the PLD at
the power on.
7-8. Main Microprocessor Circuit
QL001 is the main microprocessor which controls the
unit entirely. For more details, refer to the chapter on the
microprocessor.
7-9. Sub-microprocessor Circuit
QL500 is a sub-microprocessor. It identifies the input
signal by using QD014 and controls parameters for the
PLL, IP00C702, etc. It also controls the parameters for
r e s i z i n g .
7-2