Aries Embedded RISC-V on MAX10 Manuale d'uso - Pagina 16
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5.1.1 Intel Platform Designer (Qsys)
The Intel Platform Designer implements the RISC-V system. The CPU core and peripheral devices are
instatiated, configured and communicate via the Avalon Interconnect. Each device occupies a memory range
in the address space, the interconnect will automatically resolve the access signals.
5.1.1.1 SERV
The Serv Core implements the RV32I instruction set, an integrated memory mapped interrupt controller
provides handling for external, software and timer interrupts. The interrupt controller also provides a general
purpose time register. The following configuration parameters are avilable:
Parameter
Reset Vector
Interrupts
Timer Width
5.1.1.2 PicoRV32
The PicoRV32 core can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core and implements
a native custom interrupt controller. The following configuration parameters are avilable.
Parameter
Enable Counters
Enable Counters (64bit)
Enable Registers x16 to x31
Dual Port Registers
Two Stage Shift
Barrel Shifter
Two Cycle Compare
Two Cycle ALU
Compressed ISA
Catch Address Misalign
Catch Illegal Instruction
Enable MUL
Enable Fast MUL
Enable DIV
Chapter 5. Reference Design
Description
Address loaded into the program counter when the core starts.
Number of interrupts avilable in the interrupt controller. (Range 1 - 32)
Number of bits implemented for the timer counter. (Range 33 - 64)
Description
Enables support for RDCYCLE[H], RDTIME[H] and RDINSTRET[H] instruc-
tions.
Enables support for RDCYCLEH, RDTIMEH and RDINSTRETH instructions.
Enables support for registers x16 to x31. When disabled the core uses the
RV32E instruction set.
Increases performance for register access, but may increase the size of the
core.
Speeds up the shift operation, but increases the size of core slightly.
Implements the shift operation by using a barrel shift, which is faster, but
further increases the size of the core.
Relaxes the longest data path and improves timing, but adds an additional
clock cycle for branch instructions.
Improves timing, but adds an additional clock cycle for instructions that
use the ALU.
Enables support for the compressed (C) instruction set.
Enables circuitry for catching misaligned memory accesses.
Enables circuitry for catching illegal instructions.
Enables support for the MUL[H[SU|U]] instructions.
Increases performance for multiplication, but increases the size of the core.
Enables support for the DIV[U]/REM[U] instructions.
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