Cypress Semiconductor CY25822-2 Scheda tecnica - Pagina 2

Sfoglia online o scarica il pdf Scheda tecnica per Hardware del computer Cypress Semiconductor CY25822-2. Cypress Semiconductor CY25822-2 9. Cypress spread spectrum clock generator specification sheet

Stampa la pagina

Pin Description

Pin No.
Pin Name
1
CLKIN
2
VDD
3
GND
4
CLKOUT
5
REFOUT
6
SDATA
7
SCLOCK
8
PWRDWN#

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc., can be individually enabled or
disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Table 1. Command Code Definition
Bit
7
0 = Block read or block write operation
1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
Start
2:8
Slave address – 7 bits
9
Write = 0
10
Acknowledge from slave
11:18
Command Code – 8 bits
'00000000' stands for block operation
19
Acknowledge from slave
20:27
Byte Count – 8 bits
28
Acknowledge from slave
29:36
Data byte 1 – 8 bits
37
Acknowledge from slave
38:45
Data byte 2 – 8 bits
46
Acknowledge from slave
....
......................
....
Data Byte (N–1) –8 bits
....
Acknowledge from slave
Document #: 38-07531 Rev. **
Pin Type
Input
48-MHz or 66-MHz Clock Input.
Power
Power Supply for PLL and Outputs.
Ground
Ground for Outputs.
Output
48-MHz or 66-MHz Spread Spectrum Clock Output.
Output
Non-spread Spectrum Reference Clock Output.
2
I/O
I
C-compatible SDATA.
2
Input
I
C-compatible SCLOCK.
Output
LVTTL Input for PowerDown# Active Low.
Description
Description
Pin Description

Data Protocol

The clock driver serial protocol accepts byte write, byte read,
block write, and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code, as
described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol.The slave receiver address is 11010100 (D4h).
Block Read Protocol
Bit
1
Start
2:8
Slave address – 7 bits
9
Write = 0
10
Acknowledge from slave
11:18
Command Code – 8 bits
'00000000' stands for block operation
19
Acknowledge from slave
20
Repeat start
21:27
Slave address – 7 bits
28
Read = 1
29
Acknowledge from slave
30:37
Byte count from slave – 8 bits
38
Acknowledge
39:46
Data byte from slave – 8 bits
47
Acknowledge
48:55
Data byte from slave – 8 bits
CY25822-2
Description
Page 2 of 9
[+] Feedback