Cypress Semiconductor CY62138FV30 Scheda tecnica - Pagina 5

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Cypress Semiconductor CY62138FV30 Scheda tecnica

Switching Characteristics

Parameter
Read Cycle
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low-Z
LZOE
t
OE HIGH to High-Z
HZOE
t
CE
LZCE
t
CE
HZCE
t
CE
PU
t
CE
PD
[14]
Write Cycle
t
Write Cycle Time
WC
t
CE
SCE
t
Address Setup to Write End
AW
t
Address Hold from Write End
HA
t
Address Setup to Write Start
SA
t
WE Pulse Width
PWE
t
Data Setup to Write End
SD
t
Data Hold from Write End
HD
t
WE LOW to High-Z
HZWE
t
WE HIGH to Low-Z
LZWE
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
pulse levels of 0 to V
, and output loading of the specified I
CC(typ)
12. At any given temperature and voltage condition, t
13. t
, t
, and t
transitions are measured when the output enters a high impedance state.
HZOE
HZCE
HZWE
14. The internal write time of the memory is defined by the overlap of WE, CE
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
Document #: 001-08029 Rev. *E
(Over the Operating Range)
Description
LOW and CE
HIGH to Data Valid
1
2
[12]
[12,13]
LOW and CE
HIGH to Low Z
1
2
HIGH or CE
LOW to High-Z
1
2
LOW and CE
HIGH to Power Up
1
2
HIGH or CE
LOW to Power Down
1
2
LOW and CE
HIGH to Write End
1
2
[12, 13]
[12]
/I
OL
OH
is less than t
HZCE
LZCE
[11]
[12]
[12, 13]
as shown in the
""AC Test Loads and Waveforms" on page
, t
is less than t
, and t
HZOE
LZOE
HZWE
= V
, and CE
= V
. All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
CY62138FV30 MoBL
45 ns
Min
Max
45
45
10
45
22
5
18
10
18
0
45
45
35
35
0
0
35
25
0
18
10
CC(typ)
4" .
is less than t
for any given device.
LZWE
Page 5 of 13
®
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/2, input
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