Cypress Semiconductor CY62148ESL Scheda tecnica - Pagina 7

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Switching Waveforms

ADDRESS
DATA OUT
PREVIOUS DATA VALID
ADDRESS
CE
OE
HIGH IMPEDANCE
DATA OUT
V
CC
SUPPLY
CURRENT
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
ADDRESS
CE
WE
OE
NOTE 18
DATA IO
Notes
13. Device is continuously selected. OE, CE = V
14. WE is HIGH for read cycles.
15. Address valid before or similar to CE transition LOW.
16. Data IO is high impedance if OE = V
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
18. During this period, the IOs are in output state. Do not apply input signals.
Document #: 001-50045 Rev. **
Figure 3. Read Cycle No. 1 (Address Transition Controlled)
t
AA
t
OHA
Figure 4. Read Cycle No. 2 (OE Controlled)
t
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
50%
t
SCE
t
AW
t
SA
t
HZOE
.
IL
.
IH
t
RC
RC
[14, 15]
RC
DATA VALID
t
WC
t
PWE
t
SD
DATA VALID
CY62148ESL MoBL
[13, 14]
DATA VALID
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
50%
[16, 17]
t
HA
t
HD
Page 7 of 10
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