Cypress Semiconductor CY7C024BV Scheda tecnica - Pagina 12
Sfoglia online o scarica il pdf Scheda tecnica per Hardware del computer Cypress Semiconductor CY7C024BV. Cypress Semiconductor CY7C024BV 20. 3.3v 4k/8k/16k x 16/18 dual-port static ram
Stampa la paginaSwitching Waveforms
Figure 8. Write Cycle No. 1: R/W Controlled Timing
ADDRESS
OE
[38, 39]
CE
R/W
DATA OUT
DATA IN
Figure 9. Write Cycle No. 2: CE Controlled Timing
ADDRESS
[38, 39]
CE
R/W
DATA IN
Notes
34. R/W or CE must be HIGH during all address transitions.
35. A write occurs during the overlap (t
36. t
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
data to be placed on the bus for the required t
be as short as the specified t
PWE
38. To access RAM, CE = V
, SEM = V
IL
39. To access upper byte, CE = V
IL
To access lower byte, CE = V
IL
40. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested.
41. During this period, the IO pins are in the output state, and input signals must not be applied.
42. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06052 Rev. *J
(continued)
t
WC
t
AW
t
t
SA
[40]
t
HZWE
NOTE 41
t
WC
t
AW
t
t
SA
SCE
or t
) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
SD
.
.
IH
, UB = V
, SEM = V
.
IL
IH
, LB = V
, SEM = V
.
IL
IH
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
[34, 35, 36, 37]
[37]
t
PWE
HA
t
t
SD
[34, 35, 36, 42]
t
HA
t
t
SD
or (t
PWE
HZWE
[40]
t
HZOE
t
LZWE
NOTE 41
HD
HD
+ t
) to enable the IO drivers to turn off and
SD
Page 12 of 19
[+] Feedback