Cypress Semiconductor CY7C1012DV33 Scheda tecnica - Pagina 4

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Capacitance
Tested initially and after any design or process changes that may affect these parameters
Parameter
Description
C
Input Capacitance
IN
C
I/O Capacitance
OUT

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Θ
Thermal Resistance
JA
(junction to ambient)
Θ
Thermal Resistance
JC
(junction to case)
OUTPUT
Z 0 = 50Ω
(a)
*
Capacitive Load consists of all
components of the test environment
Note
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
V
, normal SRAM operation begins including reduction in V
DD
Document Number: 38-05610 Rev. *D
T
= 25°C, f = 1 MHz, V
A
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
Figure 2. AC Test Loads and Waveforms
50Ω
= 1.5V
V
TH
30 pF*
3.0V
90%
10%
GND
Rise Time > 1V/ns
to the data retention (V
DD
.
Test Conditions
= 3.3V
CC
Test Conditions
[4]
All input pulses
90%
10%
Fall Time:> 1V/ns
(c)
(3.0V). 100μs (t
DD
, 2.0V) voltage.
CCDR
CY7C1012DV33
Max
8
10
119-Ball
PBGA
°C/W
20.31
°C/W
8.35
R1 317 Ω
3.3V
OUTPUT
5 pF*
*Including jig
and scope
(b)
) after reaching the minimum operating
power
Page 4 of 11
Unit
pF
pF
Unit
R2
351Ω
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