Cypress Semiconductor CY7C1041DV33 Scheda tecnica - Pagina 5

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Cypress Semiconductor CY7C1041DV33 Scheda tecnica
AC Switching Characteristics
Parameter
Read Cycle
[9]
t
V
power
CC
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low-Z
LZOE
t
OE HIGH to High-Z
HZOE
t
CE LOW to Low-Z
LZCE
t
CE HIGH to High-Z
HZCE
t
CE LOW to Power Up
PU
t
CE HIGH to Power Down
PD
t
Byte Enable to Data Valid
DBE
t
Byte Enable to Low-Z
LZBE
t
Byte Disable to High-Z
HZBE
[12, 13]
Write Cycle
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Setup to Write End
AW
t
Address Hold from Write End
HA
t
Address Setup to Write Start
SA
t
WE Pulse Width
PWE
t
Data Setup to Write End
SD
t
Data Hold from Write End
HD
t
WE HIGH to Low-Z
LZWE
t
WE LOW to High-Z
HZWE
t
Byte Enable to End of Write
BW

Notes

8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
and 30-pF load capacitance.
9. t
gives the minimum amount of time that the power supply should be at typical V
POWER
10. t
, t
, t
and t
are specified with a load capacitance of 5 pF as in part (c) of
HZOE
HZCE
HZBE,
HZWE
a high impedance state.
11. At any given temperature and voltage condition, t
device.

Document #: 38-05473 Rev. *E

Over the Operating Range
Description
(Typical) to the First Access
[10, 11]
[11]
[10, 11]
[11]
[10, 11]
is less than t
, t
HZCE
LZCE
HZOE
[8]
–10 (Industrial)
Min
Max
100
10
10
3
10
5
0
5
3
5
0
10
5
0
6
10
7
7
0
0
7
5
0
3
5
7
values until the first memory access is performed.
CC
AC Test Loads and
Waveforms. Transition is measured when the outputs enter
is less than t
, t
is less than t
LZOE
HZBE
LZBE
CY7C1041DV33
–12 (Automotive)
Unit
Min
Max
μs
100
12
ns
12
ns
3
ns
12
ns
6
ns
0
ns
6
ns
3
ns
6
ns
0
ns
12
ns
6
ns
0
ns
6
ns
12
ns
8
ns
8
ns
0
ns
0
ns
8
ns
6
ns
0
ns
3
ns
6
ns
8
ns
, and t
is less than t
for any given
HZWE
LZWE
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