Cypress Semiconductor CY7C107BN Scheda tecnica

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Features
• High speed
— t
= 15 ns
AA
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
512 x 2048
4
A
ARRA Y
5
A
6
A
7
A
8
COLUMN
DECODER
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current I
Cypress Semiconductor Corporation
Document #: 001-06426 Rev. **
D
IN
D
OUT
POWER
DOWN
CE
WE
(mA)
SB2
•
198 Champion Court
1M x 1 Static RAM
Functional Description
The CY7C107BN and CY7C1007BN are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic
power-down
feature
consumption by more than 65% when deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(D
) is written into the memory location specified on the
IN
address pins (A
through A
0
19
Reading from the devices is accomplished by taking Chip
Enable (CE) LOW while Write Enable (WE) remains HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the data output
(D
) pin.
OUT
The output pin (D
) is placed in a high-impedance state
OUT
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107BN is available in a standard 400-mil-wide SOJ;
the CY7C1007BN is available in a standard 300-mil-wide SOJ
Pin Configuration
Top View
A
1
10
A
2
11
A
3
12
A
4
13
A
5
14
A
6
15
NC
7
A
8
16
A
9
17
A
10
18
A
11
19
D
12
OUT
13
WE
GND
14
7C107BN-15
7C1007BN-15
,
•
San Jose
CA 95134-1709
CY7C107BN
CY7C1007BN
that
reduces
power
).
SOJ
V
28
CC
27
A
9
26
A
8
25
A
7
24
A
6
23
A
5
22
A
4
21
NC
20
A
3
19
A
2
18
A
1
17
A
0
D
16
IN
15
CE
15
80
2
•
408-943-2600
Revised February 1, 2006
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