Cypress Semiconductor CY7C130A Scheda tecnica - Pagina 11
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Switching Waveforms
CE
Valid First:
L
ADDRESS
L, R
CE
L
CE
R
BUSY
R
CE
Valid First:
R
ADDRESS
L,R
CE
R
CE
L
BUSY
L
Left Address Valid First:
ADDRESS
L
ADDRESS
R
BUSY
R
Right Address Valid First:
ADDRESS
R
ADDRESS
L
BUSY
L
Document #: 38-06002 Rev. *E
(continued)
Figure 10. Busy Timing Diagram No. 1 (CE Arbitration)
ADDRESS MATCH
t
PS
t
BLC
ADDRESS MATCH
t
PS
t
BLC
Figure 11. Busy Timing Diagram No. 2 (Address Arbitration)
t
or t
RC
WC
ADDRESS MATCH
t
PS
t
BLA
t
or t
RC
WC
ADDRESS MATCH
t
PS
t
BLA
t
BHC
t
BHC
ADDRESS MISMATCH
t
BHA
ADDRESS MISMATCH
t
BHA
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Page 11 of 19
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