Cypress Semiconductor CY7C1332AV25 Scheda tecnica - Pagina 15

Sfoglia online o scarica il pdf Scheda tecnica per Hardware del computer Cypress Semiconductor CY7C1332AV25. Cypress Semiconductor CY7C1332AV25 19. Cypress 18-mbit (512k x 36/1mbit x 18) pipelined register-register late write specification sheet

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Switching Characteristics

Parameter
t
V
(typical) to the First Access Read or Write
Power
CC
Clock
t
Clock Cycle Time
CYC
F
Maximum Operating Frequency
MAX
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid After CLK Rise
CO
t
OE LOW to Output Valid
EOV
t
Data Output Hold After CLK Rise
DOH
t
Clock to High-Z
CHZ
t
Clock to Low-Z
CLZ
t
OE HIGH to Output High-Z
EOHZ
t
OE LOW to Output Low-Z
EOLZ
Set-Up Times
t
Address Set-Up Before CLK Rise
AS
t
Data Input Set-Up Before CLK Rise
DS
t
WE, BWS
WES
x
t
Chip Select Set-Up
CES
Hold Times
t
Address Hold After CLK Rise
AH
t
Data Input Hold After CLK Rise
DH
t
WE, BW
Hold After CLK Rise
WEH
x
t
Chip Select Hold After CLK Rise
CEH
Notes:
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
19. t
, t
CHZ
CLZ
20. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. This part has a voltage regulator that steps down the voltage internally; t
or write operation can be initiated.
Document No: 001-07844 Rev. *A
PRELIMINARY
[18, 19, 20, 21]
Description
[17, 19, 21]
[17, 18, 19, 20, 21]
[17, 18, 19, 20, 21]
[18, 19, 21]
[18, 19, 21]
Set-Up Before CLK Rise
is less than t
and t
EOHZ
EOLZ
CHZ
250
Min.
Max.
[22]
1
4.0
250
1.5
1.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
0.3
0.3
0.3
0.3
0.6
0.6
0.6
0.6
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
is the time power needs to be supplied above V
Power
CY7C1330AV25
CY7C1332AV25
200
Min.
Max.
Unit
1
ms
5.0
ns
200
MHz
1.5
ns
1.5
ns
2.25
ns
2.25
ns
0.5
ns
2.25
ns
0.5
ns
2.25
ns
0.5
ns
0.3
ns
0.3
ns
0.3
ns
0.3
ns
0.6
ns
0.6
ns
0.6
ns
0.6
ns
minimum initially before a read
DD
Page 15 of 19
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