Cypress Semiconductor CY7C1334H Scheda tecnica - Pagina 5

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Interleaved Burst Address Table
(MODE = Floating or V
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
Cycle Description Truth Table
Operation
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst) None
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
Sleep MODE
Notes:
2. X = "Don't Care." H = HIGH, L = LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies
that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW
, and WE. See Write Cycle Descriptions table.
[A:D]
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
OE is inactive or when the device is deselected, and DQs = data when OE is active.
Document #: 38-05678 Rev. *B
)
DD
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
10
00
01
01
00
[2, 3, 4, 5, 6, 7, 8]
Address
Used
CE
ZZ
None
H
None
X
External
L
Next
X
External
L
Next
X
External
L
Next
X
L
Next
X
Current
X
None
X
Linear Burst Address Table (MODE = GND)
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
10
10
11
11
00
ADV/LD
WE
BW
x
L
L
X
X
L
H
X
X
L
L
H
X
L
H
X
X
L
L
H
X
L
H
X
X
L
L
L
L
L
H
X
L
L
L
L
H
L
H
X
H
L
X
X
X
H
X
X
X
CY7C1334H
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
00
00
01
01
10
OE
CEN
CLK
DQ
X
L
L-H
Tri-State
X
L
L-H
Tri-State
L
L
L-H
Data Out (Q)
L
L
L-H
Data Out (Q)
H
L
L-H
Tri-State
H
L
L-H
Tri-State
X
L
L-H
Data In (D)
X
L
L-H
Data In (D)
X
L
L-H
Tri-State
X
L
L-H
Tri-State
X
H
L-H
X
X
X
Tri-State
= Tri-State when
[A:D]
Page 5 of 13
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