Cypress Semiconductor CY7C1339G Scheda tecnica - Pagina 5

Sfoglia online o scarica il pdf Scheda tecnica per Hardware del computer Cypress Semiconductor CY7C1339G. Cypress Semiconductor CY7C1339G 18. Cypress 4-mbit (128k x 32) pipelined sync sram specification sheet

Stampa la pagina

Cypress Semiconductor CY7C1339G Scheda tecnica

signal. Consecutive single Read cycles are supported. Once

the SRAM is deselected at clock rise by the chip select and

either ADSP or ADSC signals, its output will tri-state immedi-

ately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE

, CE

are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array. The Write signals (GW, BWE, and BW

ADV inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BW

signals. The CY7C1339G provides Byte Write capability that

is described in the Write Cycle Descriptions table. Asserting

the Byte Write Enable input (BWE) with the selected Byte

Write (BW

) input, will selectively write to only the desired

[A:D]

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed Write mechanism

has been provided to simplify the Write operations.

Because the CY7C1339G is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQs inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deserted HIGH, (3) CE

, CE

(4) the appropriate combination of the Write inputs (GW, BWE,

and BW

) are asserted active to conduct a Write to the

[A:D]

desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded

into

the

address

advancement logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to the DQs is written into the

corresponding address location in the memory core. If a Byte

Write is conducted, only the selected bytes are written. Bytes

not selected during a Byte Write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations.

Because the CY7C1339G is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

ZZ Mode Electrical Characteristics

Parameter

Snooze mode standby current

DDZZ

Device operation to ZZ

ZZS

ZZ recovery time

ZZREC

ZZ active to snooze current

ZZI

ZZ Inactive to exit snooze current

RZZI

Document #: 38-05520 Rev. *F

) and

[A:D]

, CE

are all asserted active, and

and

the

address

Description

to the DQs inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1339G provides a two-bit wraparound counter, fed

by A1, A0, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CE

, CE

remain inactive for the duration of t

returns LOW.

Interleaved Burst Address Table

(MODE = Floating or V

First

Second

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First

Second

Address

A1, A0

Test Conditions

ZZ > V

– 0.2V

ZZ > V

– 0.2V

ZZ < 0.2V

This parameter is sampled

CY7C1339G

, CE

, ADSP, and ADSC must

after the ZZ input

ZZREC

)

Third

Fourth

Address

A1, A0

Third

Fourth

Address

A1, A0

Min.

Max.

Unit

CYC

Page 5 of 18

[+] Feedback