Cypress Semiconductor CY7C1346H Scheda tecnica - Pagina 10

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Switching Characteristics
Parameter
t
V
(Typical) to the First Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid after CLK Rise
CO
t
Data Output Hold after CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Set-up Times
t
Address Set-up before CLK Rise
AS
t
ADSC, ADSP Set-up before CLK Rise
ADS
t
ADV Set-up before CLK Rise
ADVS
t
GW, BWE, BW
WES
t
Data Input Set-up before CLK Rise
DS
t
Chip Enable Set-Up before CLK Rise
CES
Hold Times
t
Address Hold after CLK Rise
AH
t
ADSP, ADSC Hold after CLK Rise
ADH
t
ADV Hold after CLK Rise
ADVH
t
GW, BWE, BW
WEH
t
Data Input Hold after CLK Rise
DH
t
Chip Enable Hold after CLK Rise
CEH
Notes:
11. Timing reference level is 1.5V when V
12. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
13. This part has a voltage regulator internally; t
can be initiated.
14. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
15. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document #: 38-05672 Rev. *B
[11, 12]
Over the Operating Range
Description
[13]
[14, 15, 16]
[14, 15, 16]
[14, 15, 16]
[14, 15, 16]
Set-up before CLK Rise
[A:D]
Hold after CLK Rise
[A:D]
= 3.3V and 1.25V when V
= 2.5V.
DDQ
DDQ
is the time that the power needs to be supplied above V
POWER
is less than t
and t
is less than t
OEHZ
OELZ
CHZ
-166
Min.
1
6.0
2.5
2.5
1.5
0
0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
(minimum) initially before a Read or Write operation
DD
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1346H
Max.
Unit
ms
ns
ns
ns
3.5
ns
ns
ns
3.5
ns
3.5
ns
ns
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 10 of 16
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