Cypress Semiconductor CY7C1353G Scheda tecnica - Pagina 13

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Document History Page
Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture
Document Number: 38-05515
REV.
ECN NO.
Issue Date
**
224363
See ECN
*A
288431
See ECN
*B
333626
See ECN
*C
418633
See ECN
*D
480124
See ECN
*E
1274724
See ECN
Document #: 38-05515 Rev. *E
Orig. of
Change
RKF
New data sheet
VBL
Deleted 66 MHz
Changed TQFP package in Ordering Information section to Pb-free TQFP
SYT
Removed 117-MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP Packages
according to JEDEC standards and updated the Pin Definitions accordingly
Modified V
V
OL,
OH
Replaced 'Snooze' with 'Sleep'
Replaced TBD's for Θ
Resistance table
Updated the Ordering Information by shading and unshading MPNs
according to availability
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
"3901 North First Street" to "198 Champion Court"
Modified test condition from V
Modified test condition from V
Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
VKN
Added the Maximum Rating for Supply Voltage on V
Updated the Ordering Information table.
VKN/AESA Corrected typo in the Ordering Information table
Description of Change
test conditions
and Θ
to their respective values on the Thermal
JA
JC
< V
< V
to V
IH
DD
IH
< V
to V
DDQ
DD
DDQ
CY7C1353G
DD
< V
DD
Relative to GND.
DDQ
Page 13 of 13
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