Cypress Semiconductor CY7C1353G Scheda tecnica - Pagina 9

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Switching Characteristics

Parameter
t
V
(Typical) to the first Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid After CLK Rise
CDV
t
Data Output Hold After CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Setup Times
t
Address Setup Before CLK Rise
AS
t
ADV/LD Setup Before CLK Rise
ALS
t
WE, BW
WES
X
t
CEN Setup Before CLK Rise
CENS
t
Data Input Setup Before CLK Rise
DS
t
Chip Enable Setup Before CLK Rise
CES
Hold Times
t
Address Hold After CLK Rise
AH
t
ADV/LD Hold after CLK Rise
ALH
t
WE, BW
WEH
X
t
CEN Hold After CLK Rise
CENH
t
Data Input Hold After CLK Rise
DH
t
Chip Enable Hold After CLK Rise
CEH
Notes:
13.This part has a voltage regulator internally; t
can be initiated.
14.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
15.At any voltage and temperature, t
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve tri-state prior to Low-Z under the same system conditions.
16.This parameter is sampled and not 100% tested.
17.Timing reference level is 1.5V when V
18.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
Document #: 38-05515 Rev. *E
Over the Operating Range
Description
[13]
[14, 15, 16]
[14, 15, 16]
[14, 15, 16]
[14, 15, 16]
Setup Before CLK Rise
Hold After CLK Rise
is the time that the power needs to be supplied above V
POWER
is less than t
and t
is less than t
OEHZ
OELZ
CHZ
=3.3V and is 1.25V when V
DDQ
DDQ
[17, 18]
–133
Min
1
7.5
2.5
2.5
2.0
0
0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
minimum initially before a read or write operation
DD
to eliminate bus contention between SRAMs when sharing the same data
CLZ
=2.5V.
CY7C1353G
–100
Max
Min
Max
1
10
4.0
4.0
6.5
8.0
2.0
0
3.5
3.5
3.5
3.5
0
3.5
3.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
Page 9 of 13
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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