Cypress Semiconductor CY7C1364C Scheda tecnica - Pagina 12
Sfoglia online o scarica il pdf Scheda tecnica per Hardware del computer Cypress Semiconductor CY7C1364C. Cypress Semiconductor CY7C1364C 19. 9-mbit (256k x 32) pipelined sync sram
Stampa la paginaSwitching Waveforms
[18]
Read Cycle Timing
t CYC
CLK
t
CH
t
t
ADS
ADH
ADSP
ADSC
t AS
t AH
ADDRESS
A1
GW, BWE,
BW[A:D]
t CES
t CEH
CE
ADV
OE
Data Out (Q)
High-Z
Note:
18. On this diagram, when CE is LOW, CE
Document #: 38-05689 Rev. *E
t
CL
t ADS
t ADH
A2
t WES
t WEH
t ADVS
t ADVH
t OEV
t OEHZ
t OELZ
t CLZ
Q(A2)
Q(A1)
t CO
is LOW, CE
is HIGH and CE
1
2
ADV
suspends
burst.
t CO
t DOH
Q(A2 + 1)
Q(A2 + 2)
is LOW. When CE is HIGH, CE
is HIGH or CE
3
1
CY7C1364C
A3
Burst continued with
new base address
Deselect
cycle
t CHZ
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Burst wraps around
to its initial state
is LOW or CE
is HIGH.
2
3
Page 12 of 18
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