Cypress Semiconductor CY7C138 Scheda tecnica - Pagina 11
Sfoglia online o scarica il pdf Scheda tecnica per Hardware del computer Cypress Semiconductor CY7C138. Cypress Semiconductor CY7C138 18. 4k x 8/9 dual-port static ram with sem, int, busy
Stampa la paginaSwitching Waveforms
CE
Valid First:
L
ADDRESS
L,R
CE
L
CE
R
BUSY
R
CE
Valid First:
R
ADDRESS
L,R
CE
R
CE
L
BUSY
L
Left Address Valid First:
ADDRESS
L
ADDRESS
R
BUSY
R
Right Address Valid First:
ADDRESS
R
ADDRESS
L
BUSY
L
Note
30. If t
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
PS
Document #: 38-06037 Rev. *D
(continued)
ADDRESS MATCH
t
PS
ADDRESS MATCH
t
PS
Figure 13. Busy Timing Diagram No. 2 (Address Arbitration)
t
or t
RC
WC
ADDRESS MATCH
t
PS
t
BLA
t
or t
RC
WC
ADDRESS MATCH
t
PS
t
BLA
t
t
BLC
BHC
t
t
BLC
BHC
ADDRESS MISMATCH
t
BHA
ADDRESS MISMATCH
t
BHA
CY7C138, CY7C139
[30]
Page 11 of 17
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