Cypress Semiconductor Perform STK14D88 Manuale - Pagina 2

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Pin Configurations

48-Pin SSOP
V
CAP
1
NC
2
A
3
14
A
4
12
A
7
5
A
6
6
A
7
5
NC
8
A
9
4
NC
10
NC
11
NC
12
TOP
V
13
SS
NC
14
NC
15
DQ
16
0
A
17
3
A
18
2
A
19
1
A
20
0
DQ
21
1
DQ
2
22
NC
23
NC
24

Pin Descriptions

Pin Name
I/O
A
-A
Input
14
0
DQ
-DQ
I/O
7
0
E
Input
W
Input
G
Input
V
Power Supply Power: 3.0V, +20%, -10%
CC
HSB
I/O
V
Power Supply AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
CAP
V
Power Supply Ground
SS
NC
No Connect
Note
1. See
"Package Diagrams"
on page 15 for detailed package size specifications.
Document Number: 001-52037 Rev. **
Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC
V
48
CC
NC
47
46
HSB
45
W
44
A
13
A
43
8
A
42
9
NC
41
A
40
11
39
NC
38
NC
37
NC
36
V
SS
35
NC
34
NC
DQ
33
6
G
32
A
31
10
30
E
29
DQ
7
28
DQ
5
DQ
27
4
DQ
26
3
V
25
CC
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address location
latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection Optional).
nonvolatile storage elements.
Unlabeled pins have no internal connections.
32-SOIC
V
1
CAP
A
2
14
A
3
12
A
4
7
A
5
6
A
6
5
A
7
4
A
8
3
TOP
NC
9
A
10
2
A
11
1
A
12
0
DQ
13
0
DQ
14
1
DQ
15
2
V
16
SS
[1]
Relative PCB Area Usage
Description
STK14D88
32
V
CC
31
HSB
30
W
29
A
13
28
A
8
A
27
9
26
A
11
25
G
24
NC
23
A
10
22
E
21
DQ
7
20
DQ
6
19
DQ
5
DQ
18
4
DQ
17
3
Page 2 of 17
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