Cypress Semiconductor STK14C88-5 Scheda tecnica - Pagina 12
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Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Parameter
Alt
[16]
t
t
AVAV
RC
[18, 19]
t
t
AVEL
SA
[18, 19]
t
t
ELEH
CW
[18, 19]
t
t
ELAX
HACE
t
RECALL
Switching Waveforms
ADDRESS
t
SA
CE
OE
DQ (DATA)
Notes
18. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-51038 Rev. **
[19]
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Figure 13. CE Controlled Software STORE/RECALL Cycle
t
RC
A
D
D
R
E
S
S
#
1
t
SCE
t
HACE
DATA VALID
35 ns
45 ns
Min
Max
Min
35
45
0
0
25
30
20
20
20
[19]
t
RC
A
D
D
R
E
S
S
#
6
t
/ t
STORE
RECALL
HIGH IMPEDANCE
DATA VALID
STK14C88-5
Unit
Max
ns
ns
ns
ns
μs
20
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