Cypress Semiconductor Set-top Box Clock Generator with VCXO CY24713 Scheda tecnica - Pagina 3

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AC Electrical Characteristics

[3]
Parameter
Description
DC
Output Duty Cycle
ER
Rising Edge Rate
0
EF
Falling Edge Rate
1
t
Clock Jitter
9
t
PLL Lock Time
10
V DD
Figure 4. Rise and Fall Time Definitions: ER = 0.6 x V
Note
3. Not 100% tested
Document #: 38-07396 Rev. *A
(V
= 3.3V)
DD
Duty Cycle is defined in
Output Clock Edge Rate, Measured from 20% to
80% of V
C
DD,
LOAD
Output Clock Edge Rate, Measured from 80% to
20% of V
C
DD,
LOAD
Peak-Peak period jitter maximum absolute jitter
Figure 2. Test Circuit
0.1 μF
OUTPUTS
GND
Figure 3. Duty Cycle Definition; DC = t2/t1
t1
t2
CLK
50%
t3
80%
CLK
20%
Conditions
Figure 3
50% of V
DD
= 15 pF
Figure
4.
= 15 pF
Figure
4.
C LOAD
50%
/t3, EF = 0.6 x V
DD
t4
CY24713
Min
Typ.
Max
45
50
55
0.8
1.4
–
0.8
1.4
–
–
200
250
–
–
3
CLK out
/t4
DD
Page 3 of 5
Unit
%
V/ns
V/ns
ps
ms
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