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ページを印刷するIV. DESIGN CONSIDERATIONS
Interfacing the Am7992B to Intel's 82586
Ethernet Controller
The AMD and Intel's Ethernet Controllers Serial Link in-
terfaces are functionally similar. The interfacing glue logic
for the Am7992B and the 82586 shown here accom-
modates the active voltage levels, set-up and hold timing
requirement of the two devices.
- Transmit Circuit:
82586
-->
Am7992B
• IRTS is inverted
for TENA
•
TXD is acceptable
for TX
• /TXC requires continuous clock; therefore, SIA's
/TEST pin is grounded.
- Receive Circuit:
Am7992B
-->
82586
•
RCLK
is inverted twice to reduce skew and to
ensure the required delay of 10 to 40ns
from the time of IRXC goes inactive (high)
to ICRS go inactive (end of packet
receive) for the 82586.
•
AX
is resynchronized with RCLK to become
RXD
•
RENA
is inverted and delayed for ICRS. A load
capacitance is added
to
increase the mini-
mum delay of the SIA's RENA with
respect to the last data bit.
•
CLSN
is inverted for ICDT and also enables the
ICRS. Intel's 586 requires ICRS active
with ICDT.
• Modified RCLK (M-RCLK) is used to reassert
RENA asynchronously as required by the
82586 at the end of packet. Start of
packet synchronization has no problem.
•
CLSN
active or RENA inactive disable Receive
path to RXD.
Note: The inverters must have fast and symmetrical rise
and fall time. The Am2965 meets these require-
ments and outputs MOS compatible logic levels.
82586 and Am7992B Interface
VCC
82586
Am7992B
29
C'i'S
TXC~6---------------------o~------~1"11 TCLK
RTS 28
12 TENA
TXD 27
~o
TX
SIA
RXC:~2~3~----~M=-~R~C~L~K~----~~~~~--~4
RCLK
680pF
XMT_t- 1 :.;:3:.-_ _ _ _ _ _
X1 8
9 Cl20MHz
X2:~~---~~~~
COL 24
40.2
3 RENA
COL~2~3~~~~
t - t - - - t - - 4
CDT 30
S74
L-+-O<:.l-f-o<:.t-+t
Q
CLK
S74
'---il---~U-----t Q
CLK
RX
22
r----+-~2~RX
RXJ--21--~~~
.---+--,-!CLSN
6 GND1
7 GND2
F
GND3~-------t
'---------
VCC
5.0jlF
Inverters: Am2965 (one package)
or: 74AS04 (two packages)
F/F: 74S74 (one package)
DTE Ground
Figure 3.
08496A-3
10
IV. DESIGN CONSIDERATIONS
Interfacing the Am7992B to Intel's 82586
Ethernet Controller
The AMD and Intel's Ethernet Controllers Serial Link in-
terfaces are functionally similar. The interfacing glue logic
for the Am7992B and the 82586 shown here accom-
modates the active voltage levels, set-up and hold timing
requirement of the two devices.
- Transmit Circuit:
82586
-->
Am7992B
• IRTS is inverted
for TENA
•
TXD is acceptable
for TX
• /TXC requires continuous clock; therefore, SIA's
/TEST pin is grounded.
- Receive Circuit:
Am7992B
-->
82586
•
RCLK
is inverted twice to reduce skew and to
ensure the required delay of 10 to 40ns
from the time of IRXC goes inactive (high)
to ICRS go inactive (end of packet
receive) for the 82586.
•
AX
is resynchronized with RCLK to become
RXD
•
RENA
is inverted and delayed for ICRS. A load
capacitance is added
to
increase the mini-
mum delay of the SIA's RENA with
respect to the last data bit.
•
CLSN
is inverted for ICDT and also enables the
ICRS. Intel's 586 requires ICRS active
with ICDT.
• Modified RCLK (M-RCLK) is used to reassert
RENA asynchronously as required by the
82586 at the end of packet. Start of
packet synchronization has no problem.
•
CLSN
active or RENA inactive disable Receive
path to RXD.
Note: The inverters must have fast and symmetrical rise
and fall time. The Am2965 meets these require-
ments and outputs MOS compatible logic levels.
82586 and Am7992B Interface
VCC
82586
Am7992B
29
C'i'S
TXC~6---------------------o~------~1"11 TCLK
RTS 28
12 TENA
TXD 27
~o
TX
SIA
RXC:~2~3~----~M=-~R~C~L~K~----~~~~~--~4
RCLK
680pF
XMT_t- 1 :.;:3:.-_ _ _ _ _ _
X1 8
9 Cl20MHz
X2:~~---~~~~
COL 24
40.2
3 RENA
COL~2~3~~~~
t - t - - - t - - 4
CDT 30
S74
L-+-O<:.l-f-o<:.t-+t
Q
CLK
S74
'---il---~U-----t Q
CLK
RX
22
r----+-~2~RX
RXJ--21--~~~
.---+--,-!CLSN
6 GND1
7 GND2
F
GND3~-------t
'---------
VCC
5.0jlF
Inverters: Am2965 (one package)
or: 74AS04 (two packages)
F/F: 74S74 (one package)
DTE Ground
Figure 3.
08496A-3
10