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- 1. Table of Contents
- 2. Safety Information
- 3. Electrostatic Discharge Senstitive (ESDS) Device Handling
- 4. Specifications
- 5. Theory of Operation
- 6. Theory of Operation
- 7. Setting up a Computer to Issue TAP Commands
- 8. Placing the Bass Module into TAP Mode
- 9. Equalizer Programming Method
- 10. Scope Photos
- 11. Scope Photos
- 12. Integrated Circuit Diagrams
- 13. Troubleshooting Guide
matic SD254175, that the Sharc, U4, has been schematically broken up into several blocks of
similar function/connection pins to make the schematic easier to follow.
The DSPs have no internal program ROM, so all executable program code must be stored in
external ROM. This function is provided by U301, a 4Mbit FLASH PROM. This FLASH is pro-
grammed at In-Circuit test of the DSP board. The FLASH also contains a Parameter Block, which
holds unit specific information, such as EQ type to implement (Double Satellite, Jewel
speaker, etc.), tracking power supply calibration info, tone control curve type, etc.
Two Synchronous Dynamic RAM ICs (U302 and U303) are also attached to the Sharc's parallel
bus. These are used as real-time RAM for the DSP.
The Sharc, FLASH, and SDRAM are all linked together with a 32 bit data bus and 20 bit address
bus, as well as the necessary handshaking and flow control lines, from the Sharc. Also on the
lowest 8 bits of the data bus is a 74LCX244 multiplexor IC which allows eight additional input/
output lines to be connected to the Sharc. These lines are used for various handshaking, serial
communications, and status info communications with the other hardware on the board. Because
this single address and data bus structure contains all the key components of the DSP board, any
shorts, opens, bridges, or damaged components on any of these lines will cause the DSP to
function incorrectly, or, most likely, not at all.
The clock for the Sharc and data bus are generated by the onboard crystal oscillator of U4 (Sharc)
and Y201. The internal instruction clock for the Sharc operates at 2x the oscillation frequency of
Y201. Because this is the sole source of clocking for the DSP, if this clock does not function, the
DSP will cease to function at all.
The Sharc, SDRAM, and FLASH all operate off the 3.3V supply rail.
2.4 Serial data interface, SmartSpeaker and TAP
Sheet 1 of SD254175
The SmartSpeaker interface to the head-end is a single wire, bidirectional serial data interface that
operates at 4800 baud, 1 start bit, 8 data bits, no parity, and 1 stop bit. The bus is open-collector,
with pull-up on the DSP board to 3.3V. This signal is connected to the head-end via pin 1 of J1.
The ground reference/return for all serial communications is pin 2 of J1.
Pins 3 and 6 of J1 form the serial RCV and XMT connections for TAP communications. Unlike
previous Lifestyle bass modules, the bass module communicates in RS-232 compliant format,
such that a TTL-to-RS232 converter is not needed. TAP communications operate at 4800 baud, 8
bits, even parity, 1 stop bit.
Two sections of the LM339 comparator U3 are used to form the serial data receivers. Since both
the TAP and SmartSpeaker receive lines share the same input line on the Sharc, only one commu-
nications mode can be supported at any given time.
Theory of Operation
13
PS18/28/35 Troubleshooting Guide
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