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Description

JH5

Data Bus

Note 9

1 NC

Note 9

2 NC

Note 9

3 NC

Note 9

4 NC

Note 9

5 NC

Note 9

6 NC

Note 9

7 NC

Note 9

8 NC

Note 9

9 D7

10 D6

11 D5

12 D4

13 D3

14 D2

15 D1

16 D0

17 RD#

18 WR#

19 ACK

Note 8

20 NC

Note 1: Mating Plug is plugged to prevent misalignment.

Note 2: DPI4 also functions as SPIDS# in SPI slave booting applications.

Note 3: Leave Unconnected.

Note 4: Boot Configuration is 001 by default (SPI Master Booting).

Note 5: Clock Configuration is 10 by default (16 x ClkIn), generally reconfigured in program code.

Note 6: Vd+1.1 is for power supply monitor only (DSP Core supply).

Note 7: Vdd is externally supplied: 3.3 to 5V (Vin for DSP Core Switching supply). Both connections must be

the same voltage.

Note 8: Leave open or supply 1.4 to 1.6M clock, typically data converter MCLK/N

Note 9: Not Connected, may be used for extended features by other dspbloks.

dspblok™ 21469 User Manual

40 GND

Description

JH7

Address Bus

Note 9

1 NC

Note 9

2 NC

Note 9

3 NC

4 A23

5 A22

6 A21

7 A20

8 A19

9 A18

10 A17

11 A16

12 A15

13 A14

14 A13

15 A12

16 A11

17 A10

18 A9

19 A8

20 A7

21 A6

22 A5

23 A4

24 A3

25 A2

26 A1

27 A0

28 MS1#

29 MS2#

30 MS3#

Description

JH6

Link Port

1 L0DAT0

2 L0DAT1

3 L0DAT2

4 L0DAT3

5 L0DAT4

6 L0DAT5

7 L0DAT6

8 L0DAT7

9 LCLK0

10 LACK0

11 L1DAT0

12 L1DAT1

13 L1DAT2

14 L1DAT3

15 L1DAT4

16 L1DAT5

17 L1DAT6

18 L1DAT7

19 LCLK1

20 LACK1

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