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reference clock is required. An onboard 100MHz oscillator can be enabled in case there is no
external reference connected. The onboard oscillator is connected to the primary reference
input (PRI_IN).
XTAL
100MHz LVPECL
Clock IN
[assembly option]
VCXO
The A/D and D/A clock outputs on the CDCE72010 should be configured as LVPECL outputs.
Another output is configured as LVDS output and connects to the FMC connector to be used
as reference clock for the D/A clock and data signals (CLK_TO_FPGA_P/N).
4.7.3 PLL design
The PLL functionality of the CDCE72010 is used to operate from an internal sampling clock.
To enable flexibility in frequency selection while maintaining high performance, a high
frequency low phase noise VCXO is used. A high frequency oscillator enables different output
frequencies after division.
The design allows different VCXO types:
1) VS-705-491.52 MHz (default)
a. enabling 245.76 MHz A/D sampling (divide by 2)
b. enabling 491.52 MHz D/A sampling (divide by 1)
2) TCO-2111-737.28 MHz (contact 4DSP)
a. enabling 245.76 MHz A/D sampling (divide by 3)
b. enabling 737.28 MHz D/A sampling (divide by 1)
January 2012
CDCE72010
AUXIN
Figure 5: Clock tree architecture
FMC150 User Manual
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r1.6
ADC
To FMC
DAC
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