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flowing in the gate-drain capacitance, C

low side FET to rise. If this voltage spike peaks beyond the threshold voltage V

Considering that the high side FET is also conducting, this can result in a potentially destructive shoot-

through event.

The GS-EVB-HB-0650603B-HD EVB uses a bipolar gate drive arrangement which is useful to mitigate

against the effects of gate-drain capacitor currents. The secondary supply voltage V

primary supply voltage V

FET. During the turn-off of period, the gate voltage will be negative with a value of:

This negative V

GS_OFF

2.5 Propagation Delay

•

= 12V

DRV

•

Input = 100kHz

•

= 10R, R

= 1R

•

Power train un-loaded. That is, VHV+ = 0V.

GS-EVB-HB-0650603B-HD TM Rev. 210712

and driver output. It will cause the voltage on the gate of the

GD,

. The zener diode, CR1, will regulate the positive turn on voltage of the GaN

DRV

= V

– V

GS_OFF

SEC

ZENER

voltage allows more margin before the threshold voltage can be reached.

Figure 5: Bi-polar gate drive schematic

Please refer to the Evaluation Board/Kit Important Notice on page # 16

GS-EVB-HB-0650603B-HD

Half Bridge Bipolar Drive Switch Board

. V

is typically 9 V.

SEC

Technical Manual

the FET will conduct.

TH,

is a function of the

SEC