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Memory Subsystem

Increasing the data transfer speed has been an important focus area in improving overall system performance. According

to the conventional approach, increasing the data transfer speed between the boards is the key to increasing the system

clock speed. One of the problems related to data transfer has always been the question of how to reduce the deviation of

the clock signals from the data signals (skew). However, a new method (Source-Synchronous method) that involves

sending the clock signal together with the data has been adopted here. This has been found to be very effective in

significantly reducing skew. By this method, data transfer at 540 MHz has been achieved.

Conventional 16-CPU class models require a board on which a crossbar switch is mounted for the connection between

multiple system boards. This requirement causes an increase in memory access latency and an increase in the number of

parts. In designing PRIMEPOWER 650 and 850, the need for this crossbar has been eliminated, and the goal of direct

connection between the system boards has been achieved.

Send side

Send clock

For the address system, a memory controller called a System Controller (SC), where four CPUs and an I/O bridge are

combined into a single unit, controls the cache. On these new models, each SC shares the control and maintains cache

coherency.

01/12/31

PRIMEPOWER 650 and 850 Technical White Paper

Data

ect

Clock

Source Synchronous method

Receive Side

Receive Clock