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DISPLAY PORT VREG
+5.0V
A
C9
U3
GND
MAX8902BATA+T
0.1uF
1
IN
R13
3
EN
1.00K
+3.3V
R15
2
1
5
POK
240
EP
GND
D3
9
2
B
C
1
3
4
6
D0+
D0-
D1+
D1-
D
2
5
GND
GND
DP_TX3_P
DP_TX3_N
1
2
D2
+3.3VDP
MBRS240LT3G
8
2
1
OUT
7
C12
R14
C13
C14
BYP
18.2K
0.1uF
10uF
10uF
6
FB
4
GS
GND
GND
R16
4.02K
GND
GND
(DP_OE)
R25
0
10[3C]
MIO_29
(DP_DOUT)
R26
0
10[3C]
MIO_27
(DP_IN)
R29
0
10[2C]
MIO_30
ESD PROTECTION
D4
TPD8S009DSMR
13 15
&
VCC
7
9
10
12
D2+
D2-
D3+
D3-
Note: dot represents
pins 13 & 15 being
8
11
connected.
GND
GND
DP_TX2_N
DP_TX2_P
2
3
DISPLAY PORT INTERFACE
DPAUX GENERATOR
+3.3V
R23
C19
2.49K
0.1uF
R24
U4
GND
1.50K
FIN1019MTCX
DP_RE_N
1
14
DE
VCC
2
13
DIN
NC
GND
3
12
NC
DOUT+
4
11
ROUT
DOUT-
5
10
NC
RIN+
6
9
NC
RIN-
7
8
DP_RE_N
GND
/RE
GND
+3.3V
C23
C24
1
0.1uF
0.1uF
GND
DPAUX_C_P
DPAUX_C_N
DP_HPD_R
3
4
5
Layout Note:
All Display Port data signals
(TX_P/N, RX_P/N) routed
to complemented signal @ 100
ohms differentially &
50 ohm single ended.
(DP_TX3P)
10[2A]
GTR_TX3_P
(DP_TX3N)
10[2A]
GTR_TX3_N
(DP_TX2P)
10[2B]
GTR_TX2_P
(DP_TX2N)
10[2B]
GTR_TX2_N
(DP_HPD)
R19
10[2C]
MIO_28
R27
100K
GND
C20
DPAUX_C_P
0.1uF
R28
49.9
R30
49.9
C21
DPAUX_C_N
0.1uF
R31
100K
+3.3V
ESD PROTECTION
+3.3V
C22
GND
D5
0.1uF
TPD4E001DRLR
VCC
+3.3V
2
4
5
IO1
IO2
IO3
IO4
GND
GND
Project Name:
Doc Num:
Sheet Title:
4
5
6
DISPLAY PORT CONNECTOR
P2
0472720001
C10
DP_TX3_P
1
0.1uF
2
C11
DP_TX3_N
3
0.1uF
C15
DP_TX2_P
4
0.1uF
5
C16
DP_TX2_N
6
0.1uF
7
8
9
10
11
12
R17
1M
GND
13
R18
1M
14
DPAUX_C_P
15
16
DPAUX_C_N
21
17
SH
10
DP_HPD_R
22
18
SH
R20
0
23
19
SH
24
+3.3VDP
20
SH
R21
100K
C17
0
0.1uF
R22
C18
0.1uF
GND
GND
GND
GND
SH_GND1
Avnet Engineering Services
PCB Rev:
BOM:
Variant:
UltraZed IO Carrier Card
1
01
Date:
Time:
SCH-US1CAR
11/9/2016
1:51:52 PM
Size:
Sheet:
03 - Display Port.SchDoc
B
3
6
A
B
C
D
02
17
of